CAV24C02, CAV24C04,
CAV24C08, CAV24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I
2
C CMOS Serial EEPROM
Description
The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively CMOS Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I
2
C
protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16
device on the same bus.
Features
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TSSOP−8
Y SUFFIX
CASE 948AL
SOIC−8
W SUFFIX
CASE 751BD
PIN CONFIGURATIONS
SOIC (W), TSSOP (Y)
CAV24C__
16 / 08 / 04 / 02
NC / NC / NC / A
0
NC / NC / A
1
/ A
1
NC / A
2
/ A
2
/ A
2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
•
•
•
•
•
•
•
•
•
•
•
Automotive Temperature Grade 1 (−40°C to +125°C)
Supports Standard and Fast I
2
C Protocol
2.5 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
CAV Prefix for Automotive and Other Applications Requiring Site
and Change Control
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
CC
(Top View)
PIN FUNCTION
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
NC
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
SCL
A
2
, A
1
, A
0
WP
CAV24Cxx
SDA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
V
SS
Figure 1. Functional Symbol
©
Semiconductor Components Industries, LLC, 2011
May, 2011
−
Rev. 2
1
Publication Order Number:
CAV24C02/D
CAV24C02, CAV24C04, CAV24C08, CAV24C16
DEVICE MARKINGS
(TSSOP−8)
CSSS
AYMXXX
G
CSSS
SSS
SSS
SSS
SSS
A
Y
M
XXX
G
= Specific Device Code, where
= 02H for CAV24C02
= 04K for CAV24C04
= 08K for CAV24C08
= 16K for CAV24C16
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Pb−Free Package
(SOIC−8)
24CSSS
AYMXXX
G
24CSSS = Specific Device Code, where
SSS = 02H for CAV24C02
SSS = 04K for CAV24C04
SSS = 08K for CAV24C08
SSS = 16K for CAV24C16
A
= Assembly Location
Y
= Production Year (Last Digit)
M
= Production Month (1−9, O, N, D)
XXX
= Last Three Digits of Assembly Lot Number
G
= Pb−Free Package
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any pin with respect to Ground (Note 1)
Ratings
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. During input transitions, voltage undershoot on any pin should not exceed
−1
V for more than 20 ns. Voltage overshoot on pins A
0
, A
1
, A
2
and WP should not exceed V
CC
+ 1 V for more than 20 ns, while voltage on the I
2
C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of V
CC
.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
A
0
, A
1
, A
2
and WP
SCL and SDA
Output Low Voltage
V
CC
> 2.5 V, I
OL
= 3 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
−0.5
0.7 x V
CC
0.7 x V
CC
T
A
=
−40°C
to +125°C
Min
Max
1
2
5
2
0.3 x V
CC
V
CC
+ 0.5
5.5
0.4
Units
mA
mA
mA
mA
V
V
V
V
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CAV24C02, CAV24C04, CAV24C08, CAV24C16
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
C
IN
(Note 4)
I
WP
(Note 5)
Parameter
SDA Pin Capacitance
Other Pins
WP Input Current
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.6 V
V
IN
< V
IH
, V
CC
= 2.5 V
V
IN
> V
IH
I
A
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.6 V
V
IN
< V
IH
, V
CC
= 2.5 V
V
IN
> V
IH
Conditions
V
IN
= 0 V, f = 1.0 MHz, V
CC
= 5.0 V
Max
8
6
130
120
80
2
50
35
25
2
mA
Units
pF
pF
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS
(Note 6) (V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
(Note 6)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 6)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 7, 8)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
6. Test conditions according to “AC Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V
CC
to 0.8 x V
CC
v
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source I
OL
= 3 mA; C
L
= 100 pF
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CAV24C02, CAV24C04, CAV24C08, CAV24C16
Power−On Reset (POR)
Each CAV24Cxx* incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAV24Cxx device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
*For common features, the CAV24C02/04/08/16 will be
referred to as CAV24Cxx.
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2:
The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP:
The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAV24Cxx supports the Inter−Integrated Circuit
2
C) Bus data transmission protocol, which defines a device
(I
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAV24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
I
2
C Bus Protocol
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A
2
, A
1
and A
0
must match the state of the external
address pins, and a
10
, a
9
and a
8
are internal address bits.
Acknowledge
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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CAV24C02, CAV24C04, CAV24C08, CAV24C16
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A
2
A
2
A
2
a
10
A
1
A
1
a
9
a
9
A
0
a
8
a
8
a
8
R/W
R/W
R/W
R/W
CAV24C02
CAV24C04
CAV24C08
CAV24C16
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
1
8
9
BUS RELEASE DELAY
(RECEIVER)
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (v t
AA
)
ACK SETUP (w t
SU:DAT
)
Figure 4. Acknowledge Timing
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
DH
t
BUF
t
HD:SDA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
HIGH
t
LOW
t
R
Figure 5. Bus Timing
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