74LVQ00
LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE
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HIGH SPEED:
t
PD
= 5.5ns (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2µA (MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
DESCRIPTION
The 74LVQ00 is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
Figure 1: Pin Connection And IEC Logic Symbols
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technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
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74LVQ00MTR
74LVQ00TTR
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July 2004
Rev. 5
1/11
74LVQ00
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
NAME AND FUNCTION
Data Inputs
Data Inputs
Data Outputs
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
A
L
L
H
H
B
L
H
L
H
Y
H
H
H
L
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
I
CC
or I
GND
DC V
CC
or Ground Current
Storage Temperature
T
stg
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
b
O
dt/dv
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
so
T
op
r
P
te
le
Input Voltage
Output Voltage
Supply Voltage (note 1)
du
o
(s
ct
-
)
bs
O
et
l
o
P
e
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
200
-65 to +150
300
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-0.5 to +7
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Unit
V
V
V
mA
mA
mA
mA
°C
°C
Parameter
Value
2 to 3.6
0 to V
CC
0 to V
CC
-55 to 125
0 to 10
Unit
V
V
V
°C
ns/V
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0V (note 2)
2/11
74LVQ00
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
T
A
= 25°C
Min.
2.0
0.8
I
O
=-50
µA
3.0
I
O
=-12 mA
I
O
=-24 mA
V
OL
Low Level Output
Voltage
I
O
=50
µA
3.0
I
O
=12 mA
I
O
=24 mA
I
I
I
CC
I
OLD
I
OHD
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
3.6
3.6
3.6
V
I
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
±
0.1
2
36
-25
0.002
0
0.1
0.36
2.9
2.58
2.99
2.9
2.48
2.2
0.1
0.44
0.55
±
1
20
Typ.
Max.
Value
-40 to 85°C
Min.
2.0
0.8
2.9
2.48
2.2
0.1
0.44
V
0.55
±
1
20
V
Max.
-55 to 125°C
Min.
2.0
0.8
Max.
V
V
Unit
V
IH
V
IL
V
OH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
3.0 to
3.6
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
V
OLP
V
OLV
V
IHD
V
ILD
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O
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
ro
P
te
le
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input (note
1, 3)
Dynamic Low
Voltage Input (note
1, 3)
du
3.3
3.3
(s
ct
-
)
so
b
O
Min.
0.3
-0.8
2
te
le
Max.
0.8
r
P
od
uc
25
-25
s)
t(
µA
µA
mA
mA
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
V
V
Unit
T
A
= 25°C
Typ.
-0.3
C
L
= 50 pF
0.8
V
3/11
74LVQ00
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.3
(*)
2.7
3.3
(*)
T
A
= 25°C
Min.
.
Typ.
6.0
5.5
0.5
0.5
Max.
11.0
8.0
1.0
1.0
Value
-40 to 85°C
Min.
Max.
12.0
9.0
1.0
1.0
-55 to 125°C
Min.
Max.
14.0
10.0
1.0
1.0
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
t
OSLH
t
OSHL
Output To Output
Skew Time (note1,
2)
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
4
24
Max.
Value
-40 to 85°C
Min.
Max.
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/4 (per gate)
Figure 3: Test Circuit
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du
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(s
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-
)
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Min.
-55 to 125°C
Max.
s)
t(
Unit
pF
pF
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
4/11
74LVQ00
Figure 4: Waveform - Propagation Delays
(f=1MHz; 50% duty cycle)
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du
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(s
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)
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5/11
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