PCI Express™ Jitter Attenuator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
874003DI-02
DATA SHEET
G
ENERAL
D
ESCRIPTION
The 874003DI-02 is a high performance Dif-ferential-to-LVDS
Jitter Attenuator designed for use in PCI Express™ systems. In
some PCI Express systems, such as those found in desktop PCs,
the PCI Express clocks are generated from a low bandwidth, high
phase noise PLL frequency synthesizer. In these systems, a jitter
attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer and
from the system board. The 874003DI-02 has a bandwidth of 3MHz.
The 3MHz provides an intermediate bandwidth that can easily track
triangular spread profiles, while providing good jitter attenuation.
The 874003DI-02 uses IDT’s 3
rd
Generation FemtoClock
TM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
•
Three differential LVDS output pairs
•
One differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 320MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 30ps (maximum)
•
Supports PCI-Express Spread-Spectrum Clocking
•
3MHz PLL loop bandwidth
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
F
EATURES
F_SEL[2:0] F
UNCTION
T
ABLE
F_SEL2
0
1
0
1
0
1
0
1
Inputs
F_SEL1
0
0
1
1
0
0
1
1
F_SEL0
0
0
0
0
1
1
1
1
Outputs
QA0, nQA0:QA1, nQA1
÷2 (default)
÷5
÷4
÷2
÷2
÷5
÷4
÷4
QB0, nQB0
÷2 (default)
÷2
÷2
÷4
÷5
÷4
÷5
÷4
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
QA1
V
DDO
QA0
nQA0
MR
F_SEL0
nc
V
DDA
F_SEL1
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nQA1
DDO
QB0
nQB0
F_SEL2
OEB
GND
nCLK
CLK
OEA
874003DI-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
874003DI-02 REVISION A 7/17/15
1
©2015 Integrated Device Technology, Inc.
874003DI-02 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 20
2, 19
3, 4
5
6,
9,
16
7
8
10
11
12
13
14
15
17, 18
Name
QA1, nQA1
V
DDO
QA0, nQA0
MR
F_SEL0,
F_SEL1,
F_SEL2
nc
V
DDA
V
DD
OEA
CLK
nCLK
GND
OEB
nQB0, QB0
Power
Output
Input
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inverted outputs
Pulldown
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pulldown
Frequency select pin for QAx/nQAx and QB0/nQB0 outputs.
LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Core supply pin.
Pullup
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Inverting differential clock input.
Power supply ground.
Pullup
Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are
active. When LOW, the QB0/nQB0 outputs are in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Input
Unused
Power
Power
Input
Input
Input
Power
Input
Output
Pulldown Non-inverting differential clock input.
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. OEA O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA
0
1
Outputs
QA0/nQA0, QA1/nQA1
High Impedance
Enabled
T
ABLE
3B. OEB O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEB
0
1
Outputs
QB0/nQB0
High Impedance
Enabled
PCI EXPRESS™ JITTER ATTENUATOR
2
REVISION A 7/17/15
874003DI-02 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.15
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
80
15
75
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
OEA, OEB
F_SEL0, F_SEL1
F_SEL2, MR
OEA, OEB
I
IL
Input Low Current
F_SEL0, F_SEL1
F_SEL2, MR
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
5
150
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
REVISION A 7/17/15
3
PCI EXPRESS™ JITTER ATTENUATOR
874003DI-02 DATA SHEET
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
275
1.2
Typical
375
1.35
Maximum
485
50
1.5
50
Units
mV
mV
V
mV
V
OS
Δ
V
OS
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tjit(cc)
tsk(o)
tsk(b)
t
R
/ t
F
odc
Parameter
Output Frequency
Cycle-to-Cycle Jitter, NOTE 1, 3
Output Skew; NOTE 2
Bank Skew; NOTE 1, 4
Output Rise/Fall Time
Output Duty Cycle
Bank A
20% to 80%
250
47
Test Conditions
Minimum
98
Typical
Maximum
320
30
185
65
700
53
Units
MHz
ps
ps
ps
ps
%
T
A
, Ambient Temperature applied using forced air flow.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: These parameters are guaranteed by characterization. Not tested in production.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
PCI EXPRESS™ JITTER ATTENUATOR
4
REVISION A 7/17/15
874003DI-02 DATA SHEET
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V LVDS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
S
KEW
B
ANK
S
KEW
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
REVISION A 7/17/15
5
PCI EXPRESS™ JITTER ATTENUATOR
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