74ALVC373
Octal D-type transparent latch; 3-state
Rev. 02 — 18 October 2007
Product data sheet
1. General description
The 74ALVC373 is an octal D-type transparent latch featuring separate D-type inputs for
each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input
and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
The 74ALVC373 is functionally identical to the 74ALVC573, but has a different pin
arrangement.
2. Features
s
s
s
s
s
s
s
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
x
JESD8-7 (1.65 V to 1.95 V)
x
JESD8-5 (2.3 V to 2.7 V)
x
JESD8B/JESD36 (2.7 V to 3.6 V)
s
ESD protection:
x
HBM JESD22-A114E exceeds 2000 V
x
MM JESD22-A 115-A exceeds 200 V
NXP Semiconductors
74ALVC373
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ALVC373D
−40 °C
to +85
°C
SO20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
SOT764-1
Type number
74ALVC373PW
−40 °C
to +85
°C
74ALVC373BQ
−40 °C
to +85
°C
DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
×
4.5
×
0.85 mm
4. Functional diagram
1
18
17
14
13
8
7
4
3
D7
D6
D5
D4
D3
D2
D1
D0
LE
11
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OE
mna881
EN
C1
19
16
11
3
15
12
9
6
5
2
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
mna880
1
Fig 1. Logic symbol
Fig 2. IEC logic symbol
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
LATCH
1 to 8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
Q4 12
Q5 15
Q6 16
Q7 19
11 LE
1 OE
mna882
Fig 3. Functional diagram
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
2 of 17
NXP Semiconductors
74ALVC373
Octal D-type transparent latch; 3-state
LE
LE
LE
D
LE
Q
mna189
Fig 4. Logic diagram (one latch)
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna883
Fig 5. Logic diagram
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
3 of 17
NXP Semiconductors
74ALVC373
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
terminal 1
index area
Q0
D0
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
001aad090
2
3
4
5
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
LE 11
D1
Q1
Q2
D2
D3
Q3
6
7
8
9
GND 10
GND
(1)
373A
1
OE
373A
GND 10
001aad089
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 6. Pin configuration SO20 and TSSOP20
Fig 7. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
D[0:7]
LE
OE
Q[0:7]
V
CC
GND
Pin description
Pin
3, 4, 7, 8, 13, 14, 17, 18
11
1
2, 5, 6, 9, 12, 15, 16, 19
20
10
Description
data input
latch enable input (active HIGH)
output enable input (active LOW)
3-state latch output
supply voltage
ground (0 V)
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
4 of 17
NXP Semiconductors
74ALVC373
Octal D-type transparent latch; 3-state
6. Functional description
Table 3.
Functional table
[1]
Input
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable
outputs
[1]
Operating modes
Internal latch
LE
H
H
L
L
X
L
Dn
L
H
l
h
X
h
L
H
L
H
X
H
Output
Qn
L
H
L
H
Z
Z
L
L
L
L
H
H
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = High-impedance OFF-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
power-down mode, V
CC
= 0 V
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[2]
[1] [2]
Conditions
V
I
< 0 V
Min
−0.5
−50
−0.5
-
−0.5
−0.5
−0.5
-
-
−100
−65
Max
+4.6
-
+4.6
±50
V
CC
+ 0.5
+4.6
+4.6
±50
100
-
+150
500
Unit
V
mA
V
mA
V
V
V
mA
mA
mA
°C
mW
output current
supply current
ground current
storage temperature
total power dissipation
V
O
= 0 V to V
CC
T
amb
=
−40 °C
to +85
°C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
For SO20 packages: above 70
°C
derate linearly with 8 mW/K.
For TSSOP20 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60
°C
derate linearly with 4.5 mW/K.
74ALVC373_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 October 2007
5 of 17
嵌入式系统
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