CAT1021, CAT1022,
CAT1023
Supervisory Circuits with
I
2
C Serial 2k-bit CMOS
EEPROM, Manual Reset and
Watchdog Timer
Description
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The CAT1021, CAT1022 and CAT1023 are complete memory and
supervisory solutions for microcontroller−based systems. A 2k−bit
serial EEPROM memory and a system power supervisor with
PDIP−8
TSSOP−8
brown−out protection are integrated together in low power CMOS
CASE 646AA
CASE 948S
2
C bus.
technology. Memory interface is via a 400 kHz I
The CAT1021 and CAT1023 provide a precision V
CC
sense circuit
and two open drain outputs: one (RESET) drives high and the other
(RESET) drives low whenever V
CC
falls below the reset threshold
voltage. The CAT1022 has only a RESET output and does not have a
SOIC−8
Write Protect input. The CAT1021 also has a Write Protect input
CASE 751BD
(WP). Write operations are disabled if WP is connected to a logic high.
All supervisors have a 1.6 second watchdog timer circuit that resets
a system to a known state if software or a hardware glitch halts or
“hangs” the system. For the CAT1021 and CAT1022, the watchdog
timer monitors the SDA signal. The CAT1023 has a separate watchdog
timer interrupt input pin, WDI.
MSOP−8
TDFN−8
CASE 846AD
CASE 511AL
The power supply monitor and reset circuit protect memory and
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
ORDERING INFORMATION
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
For Ordering Information details, see page 13.
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
both active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, the RESET pin or a separate input,
MR, can be used as an input for push−button manual reset capability.
The on−chip, 2k−bit EEPROM memory features a 16−byte page. In addition, hardware data protection is provided by a V
CC
sense circuit that prevents writes to memory whenever V
CC
falls below the reset threshold or until V
CC
reaches the reset
threshold during power up.
Available packages include an 8−pin PDIP and surface mount 8−pin SO, 8−pin TSSOP, 8−pin TDFN and 8−pin MSOP
packages. The TDFN package thickness is 0.8 mm maximum. TDFN footprint options are 3 x 3 mm.
Features
♦
•
Precision Power Supply Voltage Monitor
•
•
•
•
•
•
5 V, 3.3 V and 3 V Systems
♦
Five Threshold Voltage Options
Watchdog Timer
Active High or Low Reset
♦
Valid Reset Guaranteed at V
CC
= 1 V
400 kHz I
2
C Bus
2.7 V to 5.5 V Operation
Low Power CMOS Technology
16−Byte Page Write Buffer
•
Built−in Inadvertent Write Protection
•
•
•
•
•
•
1
♦
WP Pin (CAT1021)
1,000,000 Program/Erase Cycles
Manual Reset Input
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin DIP, SOIC, TSSOP, MSOP or TDFN (3 x 3 mm
Foot−print) Packages
♦
TDFN Max Height is 0.8 mm
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Publication Order Number:
CAT1021/D
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 18
CAT1021, CAT1022, CAT1023
Table 1. THRESHOLD VOLTAGE OPTION
Part Dash
Number
−45
−42
−30
−28
−25
Minimum
Threshold
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORDADDRESS
BU F F E R S
COLUMN
DECODERS
SENSEAMPS
SHIFT REGISTERS
SDA
STA RT/ STOP
LOGIC
2kbit
EEPROM
XDEC
WP
(C
AT1021)
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
MR
RESET
(CAT1021/23)
RESET
WDI
(CAT1023)
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CAT1021, CAT1022, CAT1023
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
MR
RESET
WP
V
SS
MR
RESET
NC
V
SS
MR
RESET
RESET
V
SS
1
2
3
4
1
2
3
4
1
2
3
4
CAT1023
CAT1022
CAT1021
8
7
6
5
8
7
6
5
8
7
6
5
V
CC
RESET
SCL
SDA
V
CC
NC
SCL
SDA
V
CC
WDI
SCL
SDA
(Bottom View)
TDFN Package: 3 mm x 3 mm
0.8mm maximum height
−
(ZD4)
V
CC
RESET
SCL
SDA
V
CC
NC
SCL
SDA
V
CC
WDI
SCL
SDA
8
7
6
5
8
7
6
5
8
7
6
5
CAT1023
CAT1022
CAT1021
1
2
3
4
1
2
3
4
1
2
3
4
MR
RESET
WP
V
SS
MR
RESET
NC
V
SS
MR
RESET
RESET
V
SS
PIN DESCRIPTION
RESET/RESET:
RESET OUTPUT
(RESET CAT1021/23 Only)
These are open drain pins and RESET can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull−down
resistor, and the RESET pin must be connected through a
pull−up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
MR:
MANUAL RESET INPUT
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset. Pulling
the MR input low will generate a Reset condition. Reset
outputs are active while MR input is low and for the reset
timeout period after MR returns to high. The input has an
internal pull up resistor.
WP
(CAT1021 Only): WRITE PROTECT INPUT
When WP input is tied to V
SS
or left unconnected write
operations to the entire array are allowed. When tied to V
CC
,
the entire array is protected. This input has an internal pull
down resistor.
WDI
(CAT1023 Only): WATCHDOG TIMER
INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET outputs
will be driven active.
Table 2. PIN FUNCTION
Pin Name
NC
RESET
V
SS
SDA
SCL
RESET
V
CC
WP
MR
WDI
No Connect
Active Low Reset Input/Output
Ground
Serial Data/Address
Clock Input
Active High Reset Output (CAT1021/23)
Power Supply
Write Protect (CAT1021 Only)
Manual Reset Input
Watchdog Timer Interrupt (CAT1023)
Function
Table 3. OPERATING TEMPERATURE RANGE
Industrial
Extended
−40°C
to 85°C
−40°C
to 125°C
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CAT1021, CAT1022, CAT1023
Table 4. CAT102X FAMILY OVERVIEW
Device
Manual Reset
Input Pin
n
n
n
n
n
n
n
n
WDI
n
n
n
Watchdog
Watchdog
Monitor Pin
SDA
SDA
WDI
n
Write
Protection
Pin
n
Independent
Auxiliary Voltage
Sense
RESET:
Active High
and LOW
n
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
n
n
n
2k
2k
2k
2k
2k
2k
2k
NOTE: For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163 data sheets.
SPECIFICATIONS
Table 5. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 s)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
−2.0
to V
CC
+ 2.0
−2.0
to 7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum
DC voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL
(Note 3)
V
IH
(Note 3)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
(SDA, RESET)
Output High Voltage
(RESET)
I
OL
= 3 mA
V
CC
= 2.7 V
I
OH
=
−0.4
mA
V
CC
= 2.7 V
V
CC
−
0.75
Test Conditions
V
IN
= GND to V
CC
V
IN
= GND to V
CC
f
SCL
= 400 kHz
V
CC
= 5.5 V
f
SCL
= 400 kHz
V
CC
= 5.5 V
V
CC
= 5.5 V
V
IN
= GND to V
CC
−0.5
0.7 x V
CC
Min
−2
−10
Typ
Max
10
10
3
1
60
0.3 x V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
V
V
V
V
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CAT1021, CAT1022, CAT1023
Table 6. D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
V
TH
Parameter
Reset Threshold
Test Conditions
CAT102x−45
(V
CC
= 5.0 V)
CAT102x−42
(V
CC
= 5.0 V)
CAT102x−30
(V
CC
= 3.3 V)
CAT102x−28
(V
CC
= 3.3 V)
CAT102x−25
(V
CC
= 3.0 V)
V
RVALID
V
RT
(Note 4)
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
Min
4.50
4.25
3.00
2.85
2.55
1.00
15
Typ
Max
4.75
4.50
3.15
3.00
2.70
V
mV
Units
V
3. V
IL
min and V
IH
max are reference values only and are not tested.
4. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Table 7. CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
OUT
(Note 5)
C
IN
(Note 5)
Output Capacitance
Input Capacitance
Test
Test Conditions
V
OUT
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
Table 8. AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(Note 6)
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R
(Note 5)
t
F
(Note 5)
t
HD; STA
t
SU; STA
t
HD; DAT
t
SU; DAT
t
SU; STO
t
AA
t
DH
t
BUF
(Note 5)
t
WC
(Note 7)
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
0.6
0.6
0
100
0.6
900
1.3
0.6
300
300
Parameter
Min
Max
400
100
Units
kHz
ns
ms
ms
ns
ns
ms
ms
ns
ns
ms
ns
ns
ms
ms
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. Test Conditions according to “AC Test Conditions” table.
7. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
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