Low Skew 1 to 4 Clock Buffer
553S
DATASHEET
Description
The 553S is a low skew, single input to four output, clock
buffer. The 553S has best in class additive phase Jitter of sub
50 fsec.
IDT makes many non-PLL and PLL based low skew output
devices as well as Zero Delay Buffers to synchronize clocks.
Contact us for all of your clocking needs.
Features
•
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•
•
•
•
•
•
•
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Low additive phase jitter RMS: 50fs
Extremely low skew outputs (50ps)
Low cost clock buffer
Packaged in 8-SOIC and small 8-DFN package, Pb-free
Input/Output clock frequency up to 200MHz
Ideal for networking clocks
Operating voltages: 1.8V to 3.3V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Extended temperature range (-40°C to +105°C)
3.3V tolerant input clock
Block Diagram
Q0
Q1
ICLK
Q2
Q3
Output Enable
553S OCTOBER 5, 2018
1
©2018 Integrated Device Technology, Inc.
553S DATASHEET
Pin Assignments
VDD
Q0
Q1
GN D
1
2
3
4
8- pi n SOI C
8
7
6
5
OE
Q3
Q2
I CLK
VDD
Q0
Q1
GND
1
2
3
4
8
7
6
5
OE
Q3
Q2
ICLK
8-pin DFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
VDD
Q0
Q1
GND
ICLK
Q2
Q3
OE
Pin
Type
Power
Output
Output
Power
Input
Output
Output
Input
Connect to +1.8V, +2.5V, or +3.3V.
Clock output 0.
Clock output 1.
Connect to ground.
Clock input.
Clock output 2.
Clock output 3.
Pin Description
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01µF should be
connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may
be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the 553S is capable of, careful attention must be paid to board layout. Essentially, all four
outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be
degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew.
LOW SKEW 1 TO 4 CLOCK BUFFER
2
OCTOBER 5, 2018
553S DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 553S. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
Item
Supply Voltage, VDD
Output Enable and All Outputs
ICLK
Ambient Operating Temperature (extended)
Storage Temperature
Junction Temperature
Soldering Temperature
3.8V
-0.5 V to VDD+0.5 V
3.465V
-40 to +105C
-65 to +150C
125C
260C
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (extended)
Power Supply Voltage (measured in respect to GND)
Min.
-40
+1.71
Typ.
Max.
+105
+3.465
Units
C
V
OCTOBER 5, 2018
3
LOW SKEW 1 TO 4 CLOCK BUFFER
553S DATASHEET
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
Conditions
Note 1
Note 1
Min.
1.71
0.7xVDD
0.7xVDD
Typ.
Max.
1.89
3.45
0.3xVDD
VDD
0.3xVDD
Units
V
V
V
V
V
V
V
mA
pF
I
OH
= -10mA
I
OL
= 10mA
No load, 135MHz
ICLK, OE pin
1.3
0.35
15
17
5
Notes: 1. Nominal switching threshold is VDD/2.
VDD = 2.5 V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
Conditions
Note 1
Note 1
Min.
2.375
0.7xVDD
0.7xVDD
Typ.
Max.
2.625
3.45
0.3xVDD
VDD
0.3xVDD
Units
V
V
V
V
V
V
V
mA
pF
I
OH
= -16mA
I
OL
= 16mA
No load, 135MHz
ICLK, OE pin
1.8
0.5
18
17
5
VDD = 3.3 V ±5%
, Ambient temperature -40° to +105°C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
Conditions
Note 1
Note 1
Min.
3.135
0.7xVDD
0.7xVDD
Typ.
Max.
3.465
VDD
0.3xVDD
VDD
0.3xVDD
Units
V
V
V
V
V
V
V
mA
pF
I
OH
= -25mA
I
OL
= 25mA
No load, 135MHz
ICLK, OE pin
2.2
0.7
22
17
5
LOW SKEW 1 TO 4 CLOCK BUFFER
4
OCTOBER 5, 2018
553S DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
Start-up Time
Output Enable Time
Output Disable Time
t
START-UP
t
EN
t
DIS
Note 2
t
OR
t
OF
Note 1
125MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2
Rising edges at VDD/2
Part start-up time for valid outputs after
VDD ramp-up
C
L
< 5pF
C
L
< 5pF
50
0.36 to 1.44V, C
L
=5pF
1.44 to 0.36V, C
L
=5pF
2.5
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
3
Max.
200
1.0
1.0
3.5
0.05
65
200
2
3
3
Units
MHz
ns
ns
ns
ps
ps
ps
ms
cycles
cycles
VDD = 2.5 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
Start-up Time
Output Enable Time
Output Disable Time
t
START-UP
t
EN
t
DIS
Note 2
t
OR
t
OF
Note 1
125MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2
Rising edges at VDD/2
Part start-up time for valid outputs after
VDD ramp-up
C
L
< 5pF
C
L
< 5pF
40
0.5 to 2.0 V, C
L
=5pF
2.0 to 0.5 V, C
L
=5pF
3
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
3.5
Max.
200
1.0
1.0
4
0.05
65
200
2
3
3
Units
MHz
ns
ns
ns
ps
ps
ps
ms
cycles
cycles
VDD = 3.3 V ±5%
, Ambient Temperature -40° to +105°C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Buffer Additive Phase Jitter, RMS
Output to Output Skew
Device to Device Skew
Start-up Time
Output Enable Time
Output Disable Time
t
START-UP
t
EN
t
DIS
Note 2
t
OR
t
OF
Note 1
125MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2
Rising edges at VDD/2
Part start-up time for valid outputs after
VDD ramp-up
C
L
< 5pF
C
L
< 5pF
25
0.66 to 2.64 V, C
L
=5pF
2.64 to 0.66 V, C
L
=5pF
2.5
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
3
Max.
200
1.0
1.0
3.5
0.05
65
200
2
3
3
Units
MHz
ns
ns
ns
ps
ps
ps
ms
cycles
cycles
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
OCTOBER 5, 2018
5
LOW SKEW 1 TO 4 CLOCK BUFFER
stm32/stm8
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