4:1 Differential-to-LVDS Clock Multiplexer
ICS854S054I
DATA SHEET
General Description
The ICS854S054I is a 4:1 Differential-to-LVDS Clock Multiplexer
which can operate up to 2.5GHz. The ICS854S054I has 4 selectable
differential clock inputs. The PCLK, nPCLK input pairs can accept
LVPECL, LVDS or CML levels. The fully differential architecture and
low propagation delay make it ideal for use in clock distribution
circuits. The select pins have internal pulldown resistors. The SEL1
pin is the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00 selects
PCLK0, nPCLK0).
Features
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High speed 4:1 differential multiplexer
One differential LVDS output pair
Four selectable differential PCLK, nPCLK input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.147ps (typical)
Part-to-part skew: 300ps (maximum)
Propagation delay: 700ps (maximum)
Supply voltage range: 3.135V to 3.465V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0
SEL1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q
nQ
GND
nPCLK3
PCLK3
nPCLK2
PCLK2
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
00 (default)
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
01
Q
ICS854S054I
16-Lead TSSOP
5.0mm x 4.4mm x 0.92mm package body
G Package
Top View
nQ
PCLK2
nPCLK2
Pulldown
Pullup/Pulldown
10
PCLK3
nPCLK3
Pulldown
Pullup/Pulldown
11
SEL1
SEL0
Pulldown
Pulldown
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
1
©2012 Integrated Device Technology, Inc.
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5, 16
6, 7
9
10
11
12
8, 13
14, 15
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0, SEL1
PCLK2
nPCLK2
PCLK3
nPCLK3
GND
nQ, Q
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Power
Output
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
DD
/2 default when left floating.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
VDD
/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
75
50
Maximum
Units
pF
k
Ω
k
Ω
Table 3. Clock Input Function Table
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Q
PCLK0
PCLK1
PCLK2
PCLK3
Outputs
nQ
nPCLK0
nPCLK1
nPCLK2
nPCLK3
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
2
©2012 Integrated Device Technology, Inc.
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
100°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
57
Maximum
3.465
68
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL[1:0]
SEL[1:0]
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-10
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. Differential LVPECL Input DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
PCLK[0:3],
nPCLK[0:3]
PCLK[0:3]
Input Low Current
nPCLK[0:3]
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
0.15
GND + 1.2
1.2
V
DD
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
3
©2012 Integrated Device Technology, Inc.
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Table 4D. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.28
Test Conditions
Minimum
247
Typical
380
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
t
PD
tjit(Ø)
tsk(pp)
tsk(i)
t
R
/ t
F
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter,
RMS; Refer to Additive Phase
Jitter Section
Part-to-Part Skew; NOTE 2, 3
Input Skew
Output Rise/Fall Time
MUX Isolation; NOTE 4
20% to 80%
155.52MHz, V
PP
= 800mV
70
10
150
86
155.52MHz, Integration Range:
12kHz – 20MHz
295
470
0.147
300
50
250
Test Conditions
Minimum
Typical
Maximum
2.5
700
Units
GHz
ps
ps
ps
ps
ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured
≤
1.0GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See
Parameter Measurement Information
for MUX Isolation diagram.
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
4
©2012 Integrated Device Technology, Inc.
ICS854S054I Data Sheet
4:1, DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100 as the input source.
ICS854S054AGI REVISION A SEPTEMBER 28, 2012
5
©2012 Integrated Device Technology, Inc.
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