HIGH-SPEED
128K x 9 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT7019L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
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True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7019L
Active: 1W (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT7019 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading more
than one device
◆
◆
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◆
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◆
◆
◆
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-8L
I/O
Control
I/O
Control
I/O
0-8R
BUSY
L
(1,2)
BUSY
R
128Kx9
MEMORY
ARRAY
7019
17
17
(1,2)
A
16L
A
0L
Address
Decoder
Address
Decoder
A
16R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4840 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/S = V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2017
DSC-4840/7
1
©2017 Integrated Device Technology, Inc.
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT7019 is a high-speed 128K x 9 Dual-Port Static RAM. The
IDT7019 is designed to be used as a stand-alone 1152K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-
more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM
approach in 18-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (CE
0
and CE
1
) permit the on-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only1W of power.
The IDT7019 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
Pin Configurations
(1,2,3)
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
A
16R
GND
NC
NC
NC
NC
CE
0R
CE
1R
SEM
R
R/W
R
OE
R
GND
GND
NC
NC
NC
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
INT
R
BUSY
R
M/S
GND
BUSY
L
INT
L
NC
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
NC
NC
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1 2
3
4
5
6
7
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
7019
PN100
(4)
NC
NC
I/O
8R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
Vcc
I/O
2R
I/O
1R
I/O
0R
GND
Vcc
I/O
0L
I/O1
L
GND
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
GND
4840 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
A
16L
Vcc
NC
NC
NC
NC
CE
0L
CE
1L
SEM
L
R/W
L
OE
L
GND
NC
NC
2
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
16L
I/O
0L
- I/O
8L
SEM
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
16R
I/O
0R
- I/O
8R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
4840 tbl 01
Maximum Operating Temperature
and Supply Voltage
Grade
Military
Commercial
Industrial
Ambient
Temperature
(1)
-55
O
C to +125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
4840 tbl 03
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
4840 tbl 04
Absolute Maximum Ratings
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +7.0
(1)
Unit
V
V
IL
Military
-0.5 to +7.0
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
o
Capacitance
Symbol
C
IN
C
OUT
(T
A
= +25°C, f = 1.0MHz)
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4840 tbl 05
mA
4840 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
3
6.42
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Chip Enable
(1,2)
CE
L
CE
0
V
IL
< 0.2V
V
IH
X
H
>V
CC
-0.2V
X
CE
1
V
IH
>V
CC
-0.2V
X
V
IL
X
<0.2V
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
4840 tbl 06
Mode
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE
is a reference only.
2. 'H' = V
IH
and 'L' = V
IL
.
3. CMOS standby requires 'X' to be either < 0.2V or > V
CC
- 0.2V.
Truth Table II: Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-8
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to memory
Read memory
Outputs Disabled
4840 drw 07
Mode
NOTES:
1. A
0L
– A
16L
≠
A
0R
– A
16R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control
(1)
Inputs
CE
(2)
H
H
L
R/W
H
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-8
DATA
OUT
DATA
IN
______
Mode
Read Semaphore Flag Data Out
Write I/O
0
into Semaphore Flag
Not Allowed
4840 tbl 08
↑
X
NOTES:
1. There are eight semaphore flags written to via I/O
0
and read from all the I/Os (I/O
0
-I/O
8
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
4
IDT7019L
High-Speed 128K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(2)
(V
CC
= 5.0V ± 10%)
7019L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4840 tbl 09
2.4
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
CC
= 5.0V ± 10%)
7019L15
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Test Condition
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(2)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(2)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(4)
Active Port Outputs Disabled,
f=f
MAX
(2)
,
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V, V
IN
> V
CC
- 0.2V
or V
IN
< 0.2V, f = 0
(3)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(4)
,
SEM
R
=
SEM
L
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V,
Active Port Outp uts Disabled , f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
L
L
L
L
L
L
L
L
L
L
Typ.
(1)
Max
220
____
7019L20
Com'l & Ind
Typ.
(1)
Max
200
200
50
50
130
130
0.2
0.2
120
120
300
360
75
120
195
235
3.0
3.0
190
230
4840 tbl 10
Unit
mA
340
____
I
SB1
65
____
100
____
mA
I
SB2
145
____
225
____
mA
I
SB3
0.2
____
3.0
____
mA
I
SB4
135
____
220
____
mA
NOTES:
1. V
CC
= 5V, T
A
= +25°C, and are not production tested. I
CCDC
= 120mA (Typ.)
2. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ t
RC,
and using “AC Test Conditions” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
5
6.42
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