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74ALVCH16374DGG,51: 产品描述Flip Flops 3.3V 16-BIT POS; 产品类别半导体逻辑; 文件大小713KB，共17页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com

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74ALVCH16374DGG,51概述

Flip Flops 3.3V 16-BIT POS

74ALVCH16374DGG,51规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	NXP(恩智浦)
产品种类 Product Category	Flip Flops
Number of Circuits	2
Logic Family	ALVC
Logic Type	D-Type Edge Triggered Flip-Flop
Polarity	Non-Inverting
Input Type	Single-Ended
输出类型 Output Type	3-State
传播延迟时间 Propagation Delay Time	2.3 ns @ 3.3 V
High Level Output Current	- 24 mA
Low Level Output Current	24 mA
电源电压-最小 Supply Voltage - Min	1.2 V
电源电压-最大 Supply Voltage - Max	3.6 V
最小工作温度 Minimum Operating Temperature	- 40 C
最大工作温度 Maximum Operating Temperature	+ 85 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	TSSOP-48
Function	D-Type Bus Interface
Quiescent Current	200 nA
Number of Channels	16
Number of Input Lines	8
Number of Output Lines	8
工作电源电压 Operating Supply Voltage	1.8 V, 2.5 V, 3.3 V
工厂包装数量 Factory Pack Quantity	39

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74ALVCH16374

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Rev. 5 — 9 July 2012

Product data sheet

1. General description

The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for

each flip-flop and 3-state outputs for bus oriented applications.

Incorporates bus hold data inputs which eliminate the need for external pull-up or

pull-down resistors to hold unused inputs.

The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP)

input and an output enable (OE) are provided per 8-bit section.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold

time requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is

HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not

affect the state of the flip-flops.

2. Features and benefits



Wide supply voltage range from 1.2 V to 3.6 V

Complies with JEDEC standard JESD8-B

CMOS low power consumption

MULTIBYTE flow-through standard pin-out architecture

Low inductance multiple V

and GND pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold

Output drive capability 50



transmission lines at 85

C

Current drive

24

mA at V

= 3.0 V

74ALVCH16374DGG,51相似产品对比

	74ALVCH16374DGG,51	74ALVCH16374DL,118	74ALVCH16374DGG:51
描述	Flip Flops 3.3V 16-BIT POS	Flip Flops 3.3V 16-BIT POS	Flip Flops 3.3V 16-BIT POS
Brand Name	-	NXP Semiconductor	NXP Semiconductor
是否Rohs认证	-	符合	符合
厂商名称	-	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	-	SSOP	TSSOP
包装说明	-	SSOP, SSOP48,.4	TSSOP, TSSOP48,.3,20
针数	-	48	48
制造商包装代码	-	SOT370-1	SOT362-1
Reach Compliance Code	-	compliant	unknown
系列	-	ALVC/VCX/A	ALVC/VCX/A
JESD-30 代码	-	R-PDSO-G48	R-PDSO-G48
JESD-609代码	-	e4	e4
长度	-	15.875 mm	12.5 mm
负载电容（CL）	-	50 pF	50 pF
逻辑集成电路类型	-	BUS DRIVER	BUS DRIVER
最大频率@ Nom-Sup	-	200000000 Hz	200000000 Hz
最大I（ol）	-	0.024 A	0.024 A
湿度敏感等级	-	1	1
位数	-	8	8
功能数量	-	2	2
端口数量	-	2	2
端子数量	-	48	48
最高工作温度	-	85 °C	85 °C
最低工作温度	-	-40 °C	-40 °C
输出特性	-	3-STATE	3-STATE
输出极性	-	TRUE	TRUE
封装主体材料	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	-	SSOP	TSSOP
封装等效代码	-	SSOP48,.4	TSSOP48,.3,20
封装形状	-	RECTANGULAR	RECTANGULAR
封装形式	-	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法	-	TAPE AND REEL	TAPE AND REEL
峰值回流温度（摄氏度）	-	260	260
电源	-	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	-	3.4 ns	3.4 ns
传播延迟（tpd）	-	6.5 ns	6.5 ns
认证状态	-	Not Qualified	Not Qualified
座面最大高度	-	2.8 mm	1.2 mm
最大供电电压 (Vsup)	-	3.6 V	3.6 V
最小供电电压 (Vsup)	-	1.2 V	1.2 V
标称供电电压 (Vsup)	-	3.3 V	3.3 V
表面贴装	-	YES	YES
技术	-	CMOS	CMOS
温度等级	-	INDUSTRIAL	INDUSTRIAL
端子面层	-	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	-	GULL WING	GULL WING
端子节距	-	0.635 mm	0.5 mm
端子位置	-	DUAL	DUAL
处于峰值回流温度下的最长时间	-	30	30
触发器类型	-	POSITIVE EDGE	POSITIVE EDGE
宽度	-	7.5 mm	6.1 mm

74ALVCH16374DGG,51

74ALVCH16374DGG,51概述

74ALVCH16374DGG,51规格参数

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