Differential Clock/Data Multiplexer
Datasheet
831724
General Description
The 831724 is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has two differential, selectable clock/data inputs. The
selected input signal is distributed to four low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831724 is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831724 ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831724 supports the clock multiplexing and
distribution of PCI Express Generation 1, 2, and 3 clock signals.
Features
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2:1 differential clock/data multiplexer with fanout
Two selectable, differential inputs
Each differential input pair can accept the following levels: HCSL,
LVDS, LVPECL.
Four differential HCSL outputs
Maximum input/output clock frequency: 350MHz
Maximum input/output data rate: 700Mb/s (NRZ)
LVCMOS interface levels for all control inputs
PCI Express Gen 1,2,3 jitter compliant
Input skew: 165ps (maximum)
Output skew: 175ps (maximum)
Part-to-part skew: 450ps (maximum)
Full 3.3V supply voltage
Available in lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
Block Diagram
IREF
Pulldown
Pin Assignment
QA
nQA
32 31 30 29 28 27 26 25
V
DD
nOED
CLK0
nCLK0
CLK1
nCLK1
nOEA
V
DD
1
2
3
4
5
6
7
8
9
V
DD
QD
IREF
GND
nQD
nQC
V
DD
QC
V
DD
CLK0
nCLK0
CLK1
nCLK1
Pullup/down
Pulldown
Pullup/down
0
1
QB
nQB
QC
nQC
QD
nQD
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nOEB
nQB
GND
nQA
V
DD
QA
QB
nc
nOEC
nc
nc
nc
nc
SEL
nc
Pulldown
Pullup
Pullup
Pullup
Pullup
831724I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
SEL
©2016 Integrated Device Technology, Inc
1
Revision B November 16, 2016
831724 Datasheet
Table 1. Pin Descriptions
Number
1, 8, 9, 15,
26, 32
2
3
4
5
6
7
10, 11
12, 29
13, 14
16
17, 19, 20,
21, 22, 24
18
23
25
27, 28
30, 31
Name
V
DD
nOED
CLK0
nCLK0
CLK1
nCLK1
nOEA
QA, nQA
GND
QB, nQB
nOEB
nc
SEL
nOEC
IREF
QC, nQC
QD, nQD
Power
Input
Input
Input
Input
Input
Input
Output
Power
Output
Input
Unused
Input
Input
Input
Output
Output
Pulldown
Pullup
Pullup
Pullup
Pulldown
Pulldown/Pullup
Pulldown
Pulldown/Pullup
Pullup
Type
Description
Positive power supply pins.
Output enable for the QD output. See Table 3D for function. LVCMOS/LVTTL
interface levels.
Non-inverting clock/data input 0.
Inverting differential clock input 0. V
DD
/2 default when left floating.
Non-inverting clock/data input 1.
Inverting differential clock input 1. V
DD
/2 default when left floating.
Output enable for the QA output. See Table 3A for function. LVCMOS/LVTTL
interface levels.
Differential output pair A. HCSL interface levels.
Power supply ground.
Differential output pair B. HCSL interface levels.
Output enable for the QB output. See Table 3B for function. LVCMOS/LVTTL
interface levels.
No connect pins.
Input select. See Table 3E for function.
LVCMOS/LVTTL interface levels.
Output enable for the QC output. See Table 3C for function. LVCMOS/LVTTL
interface levels.
An external fixed precision resistor (475
) from this pin to ground provides a
reference current used for the differential current-mode QX, nQX outputs.
Differential output pair C. HCSL interface levels.
Differential output pair D. HCSL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc
2
Revision B November 16, 2016
831724 Datasheet
Function Tables
Table 3A. nOEA Configuration Table
Input
nOEA
0
1 (default)
Operation
Output QA, nQA is enabled.
Output QA, nQA is in high-impedance state.
Table 3B. nOEB Configuration Table
Input
nOEB
0
1 (default)
Operation
Output QB, nQB is enabled.
Output QB, nQB is in high-impedance state.
NOTE: nOEA is an asynchronous control.
Table 3C. nOEC Configuration Table
Input
nOEC
0
1 (default)
Operation
Output QC, nQC is enabled.
Output QC, nQC is in high-impedance state.
NOTE: nOEB is an asynchronous control.
Table 3D. nOED Configuration Table
Input
nOED
0
1 (default)
Operation
Output QD, nQD is enabled.
Output QD, nQD is in high-impedance state.
NOTE: nOEC is an asynchronous control.
NOTE: nOED is an asynchronous control.
Table 3E. SEL Configuration Table
Input
SEL
0 (default)
1
CLK0, nCLK0
CLK1, nCLK1
Selected Input
NOTE: SEL is an asynchronous control
©2016 Integrated Device Technology, Inc
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Revision B November 16, 2016
831724 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
37°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
128
Units
V
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
nOEA, nOEB,
nOEC, nOED
SEL
nOEA, nOEB,
nOEC, nOED
SEL
V
IN =
V
DD
V
IN =
V
DD
V
IN
= 0V
V
IN
= 0V
-150
-5
Test Conditions
Minimum
2.4
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
Input High Current
I
IL
Input Low Current
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
CLK0, nCLK0, CLK1, nCLK1
CLK0, CLK1
nCLK0, nCLK1
Test Conditions
V
IN =
V
DD
= 3.3V ± 0.3V
V
DD
= 3.3V ± 0.3V, V
IN
= 0V
V
DD
= 3.3V ± 0.3V, V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
4
Revision B November 16, 2016
831724 Datasheet
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
t
j
(PCIe Gen 1)
t
REFCLK_HF_RMS
(PCIe Gen 2)
t
REFCLK_LF_RMS
(PCIe Gen 2)
t
REFCLK_RMS
(PCIe Gen 3)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz,
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
11.48
Maximum
27
PCIe Industry
Specification
86
Units
ps
0.76
1.0
3.1
ps
0.15
1.3
3.0
ps
0.16
0.4
0.8
ps
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. The phase noise is dependent on the input signal source. The input signal was generated using a
Tektronix HFS9000 Stimulus System. For additional information, refer to the
PCI Express Application Note section
in the datasheet.
NOTE 1:
Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 2:
RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High
Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 3:
RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the
PCI Express
Base Specification Revision 0.7, October 2009
and is subject to change pending the final release version of the specification.
NOTE 4:
This parameter is guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
5
Revision B November 16, 2016
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