LNBH21
LNB SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I
2
C INTERFACE
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COMPLETE INTERFACE BETWEEN LNB
AND I
2
C
TM
BUS
BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION AND
HIGH EFFICIENCY (Typ. 94% @ 750mA)
TWO SELECTABLE OUTPUT CURRENT
LIMIT (450mA / 750mA)
BOTH COMPLIANT WITH EUTELSAT AND
DIRECT OUTPUT VOLTAGE
SPECIFICATION
ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR SUITS WIDELY ACCEPTED
STANDARDS
FAST OSCILLATOR START-UP FACILITATES
DiSEqC
TM
ENCODING
BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqC
TM
2.0
SEMI-LOWDROP POST REGULATOR AND
HIGH EFFICIENCY STEP-UP PWM FOR
LOW POWER LOSS: Typ. 0.56W @ 125mA
TWO OUTPUT PINS SUITABLE TO BYPASS
THE OUTPUT R-L FILTER AND AVOID ANY
TONE DISTORSION (R-L FILTER AS PER
DiSEqC 2.0 SPECs, see application circuit on
pag. 5)
CABLE LENGTH DIGITAL COMPENSATION
OVERLOAD AND OVER-TEMPERATURE
INTERNAL PROTECTIONS
PowerSO-20
s
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OVERLOAD AND OVER-TEMPERATURE I
2
C
DIAGNOSTIC BITs
LNB SHORT CIRCUIT SOA PROTECTION
WITH I
2
C DIAGNOSTIC BIT
+/- 4KV ESD TOLERANT ON INPUT/
OUTPUT POWER PINS
DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBH21 is a
monolithic voltage regulator and interface IC,
assembled in POWER SO-20, specifically
designed to provide the 13/18V power supply and
the 22KHz tone signalling to the LNB
downconverter in the antenna or to the multiswitch
box. In this application field, it offers a complete
solution with extremely low component count, low
power dissipation together with simple design and
I
2
C
TM
standard interfacing.
BLOCK DIAGRAM
Gate
LNBH21
Step-up PWM
Controller
Vup-Feedback
Sense
VoTX
Vup
VoRX
Vcc
Byp
Preregul.+
U.V.lockout
+P.ON res.
Linear Post-reg
+Modulator
+Protections
ISEL
EXTM
SDA
SCL
V Select
I²C interf. Enable
Diagnostics
ADDR
TEN
22KHz
Oscill.
Tone
Detector
DETIN
DSQOUT
DSQIN
April 2004
1/20
LNBH21
TABLE A: PIN CONFIGURATIONS
PIN N°
18
17
16
19
SYMBOL
V
CC
GATE
SENSE
V
UP
NAME
Supply Input
External Switch Gate
Current Sense Input
Step-up Voltage
FUNCTION
8V to 15V IC supply. A 220µF bypass capacitor to GND with a 470nF
(ceramic) in parallel is recommended
External MOS switch Gate connection of the step-up converter
DC/DC Current Sense comparator input. Connected to current
sensing resistor
Input of the linear post-regulator. The voltage on this pin is monitored
by internal step-ut controller to keep a minimum dropout across the
linear pass transistor
RX Output to the LNB in DiSEqC 2.0 application. See truth tables for
voltage selections on page 8 and description on page 5.
Bidirectional data from/to I
2
C bus.
Clock from I
2
C bus.
When the TEN bit of the System Register is LOW, this pin will accept
the DiSEqC code from the main
µcontroller.
The LNBH21 will use this
code to modulate the internally generated 22kHz carrier. Set to GND
this pin if not used.
22kHz Tone Detector Input. Must be AC coupled to the DiSEcQ 2.0
bus.
Open drain output of the tone Detector to the main
µcontroller
for
DiSEcQ 2.0 data decoding. It is LOW when tone is detected.
External Modulation Input acts on V
O
TX. Needs DC decoupling to the
AC source. If not used, can be left open.
Pins Connected to Ground.
Needed for internal preregulator filtering
Set high or floating for Iout<=750mA, connect to ground for
I
OUT
≤
450mA.
4
7
V
O
TX
ADDR
Output Port during
22KHz Tone TX
Address Setting
Output of the linear post-regulator/modulator to the LNB. See truth
tables for voltage selections.
Four I
2
C bus addresses available by setting the Address Pin level
voltage. See address pin characteristics table.
2
12
13
14
V
O
RX
SDA
SCL
DSQIN
Output Port during
22KHz Tone RX
Serial Data
Serial Clock
DiSEqC Input
9
15
5
1, 6, 10,
11, 20
8
3
DETIN
Tone Detector Input
DSQOUT DiSEqC Output
EXTM
GND
BYP
ISEL
External Modulator
Ground
Bypass Capacitor
Current Limit Select
3/20
LNBH21
APPLICATION INFORMATION
This IC has a built in DC/DC step-up controller that, from a single supply source ranging from 8 to 15V,
generates the voltages (V
UP
) that let the linear post-regulator to work at a minimum dissipated power of
1.65W typ. @ 750mA load (the linear regulator drop voltage is internally kept at: V
UP
-V
O
=2.2V typ.). An
UnderVoltage Lockout circuit will disable the whole circuit when the supplied V
CC
drops below a fixed
threshold (6.7V typically). The internal 22KHz tone generator is factory trimmed in accordance to the
standards, and can be controlled either by the I
2
C
TM
interface or by a dedicated pin (DSQIN) that allows
immediate DiSEqC
TM
data encoding (*). When the TEN (Tone ENable) I
2
C bit it is set to HIGH, a
continuous 22KHz tone is generated on the output regardless of the DSQIN pin logic status.
The TEN bit must be set LOW when the DSQIN pin is used for DiSEqC
TM
encoding. The fully
bi-directional DiSEqC
TM
2.0 interfacing is completed by the built-in 22KHz tone detector. Its input pin
(DETIN) must be AC coupled to the DiSEqC
TM
bus, and the extracted PWK data are available on the
DSQOUT pin (*).
To comply to the bi-directional DiSEqC
TM
2.0 bus hardware requirements an output R-L filter is needed.
The LNBH21 is provided with two output pins: the V
O
TX to be used during the tone transmission and the
V
O
RX to be used when the tone is received. This allows the 22KHz Tone to pass without any losses due
to the R-L filter impedance (see DiSeqC 2.0 application circuit on page 5). In DiSeqC 2.0 applications
during the 22KHz transmission activated by DSQIN pin (or TEN I
2
C bit), the V
O
TX pin must be
preventively set ON by the TTX I
2
C bit and, both the 13/18V power supply and the 22KHz tone, are
provided by mean of V
O
TX output. As soon as the tone transmission is expired, the V
O
TX must be set to
OFF by setting the TTX I
2
C bit to zero and the 13/18V power supply is provided to the LNB by the V
O
RX
pin through the R-L filter. When the LNBH21 is used in DiSeqC 1.x applications the R-L filter is not
required (see DiSeqC 1.x application circuit on pag.5), the TTX I
2
C bit must be kept always to HIGH so
that, the V
O
TX output pin can provide both the 13/18V power supply and the 22KHz tone, enabled by
DSQIN pin or by TEN I
2
C bit.
All the functions of this IC are controlled via I
2
C TM bus by writing 6 bits on the System Register (SR, 8
bits). The same register can be read back, and two bits will report the diagnostic status. When the IC is put
in Stand-by (EN bit LOW), the power blocks are disabled. When the regulator blocks are active (EN bit
HIGH), the output can be logic controlled to be 13 or 18 V by mean of the V
SEL
bit (Voltage SELect) for
remote controlling of non-DiSEqC LNBs.
Additionally, the LNBH21 is provided with the LLC I
2
C bit that increase the selected voltage value (+1V
when V
SEL
=0 and +1.5V when V
SEL
=1) to compensate for the excess voltage drop along the coaxial
cable (LLC bit HIGH).
By mean of the LLC bit, the LNBH21 is also compliant to the American LNB power supply standards that
require the higher output voltage level to 19.5V (typ.) (instead of 18V), by simply setting the LLC=1 when
V
SEL
=1.
In order to improve design flexibility and to allow implementation of newcoming LNB remote control
standards, an analogic modulation input pin is available (EXTM). An appropriate DC blocking capacitor
must be used to couple the modulating signal source to the EXTM pin. Also in this case, the V
O
TX output
must be set ON during the tone transmission by setting the TTX bit high. When external modulation is not
used, the relevant pin can be left open.
The current limitation block is SOA type and it is possible to select two current limit thresholds, by the
dedicated I
SEL
pin. The higher threshold is in the range of 750mA to 1A if the I
SEL
is left floating or
connected a voltage > 3.3V. The lower threshold is in the range of 450mA to 700mA when the I
SEL
pin is
connected to ground. When the output port is shorted to ground, the SOA current limitation block limits the
short circuit current (I
SC
) at typically 400mA or 200mA respectively for V
O
13V or 18V, to reduce the power
dissipation. Moreover, it is possible to set the Short Circuit Current protection either statically (simple
current clamp) or dynamically by the PCL bit of the I
2
C SR; when the PCL (Pulsed Current Limiting) bit is
set to LOW, the overcurrent protection circuit works dynamically, as soon as an overload is detected, the
output is shut-down for a time T
OFF
, typically 900ms. Simultaneously the OLF bit of the System Register
is set to HIGH. After this time has elapsed, the output is resumed for a time T
ON
=1/10T
OFF
(typ.). At the
end of T
ON
, if the overload is still detected, the protection circuit will cycle again through T
OFF
and T
ON
. At
the end of a full T
ON
in which no overload is detected, normal operation is resumed and the OLF bit is
reset to LOW. Typical T
ON
+T
OFF
time is 990ms and it is determined by an internal timer. This dynamic
operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent
power-on start up in most conditions.
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