February 1997
NDS352AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These P -Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage applications
such as notebook computer power management, portable
electronics, and other battery powered circuits where fast
high-side switching, and low in-line power loss are needed in a
very small outline surface mount package.
Features
-0.9 A, -30 V. R
DS(ON)
= 0.5
Ω
@ V
GS
= -4.5 V
R
DS(ON)
= 0.3
Ω
@ V
GS
= -10 V.
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOT
TM
-3 design for superior thermal
and electrical capabilities.
High density cell design for extremely low R
DS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
Parameter
Drain-Source Voltage
T
A
= 25°C unless otherwise noted
NDS352AP
-30
±20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
±0.9
±10
P
D
T
J
,T
STG
Maximum Power Dissipation
(Note 1a)
(Note 1b)
0.5
0.46
-55 to 150
W
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
250
75
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS352AP Rev.D
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= -250 µA
V
DS
= -24 V, V
GS
= 0 V
T
J
=125°C
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
-30
-1
-10
100
-100
V
µA
µA
nA
nA
ON CHARACTERISTICS
(Note 2)
V
GS(th)
R
DS(ON)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250 µA
T
J
=125°C
Static Drain-Source On-Resistance
V
GS
= -4.5 V, I
D
= -0.9 A
T
J
=125°C
V
GS
= -10 V, I
D
= -1 A
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
On-State Drain Current
V
GS
= -4.5 V, V
DS
= -5 V
V
DS
= -5 V, I
D
= -0.9 A
V
DS
= -15 V, V
GS
= 0 V,
f = 1.0 MHz
-2
1.9
-0.8
-0.5
-1.7
-1.4
0.45
0.65
0.25
-2.5
-2.2
0.5
0.7
0.3
A
S
V
Ω
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
DYNAMIC CHARACTERISTICS
135
88
40
pF
pF
pF
SWITCHING CHARACTERISTICS
(Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= -10 V, I
D
= -0.9 A,
V
GS
= -4.5 V
V
DD
= -10 V, I
D
= -1 A,
V
GS
= -10 V, R
GEN
= 50
Ω
V
DD
= -6 V, I
D
= -1 A,
V
GS
= -4.5 V, R
GEN
= 6
Ω
5
17
35
30
10
30
70
60
ns
ns
ns
ns
ns
ns
ns
ns
nC
nC
nC
8
16
35
30
2
0.5
1
15
30
90
90
3
Q
g
Q
gs
Q
gd
NDS352AP Rev.D
Electrical Characteristics
(T
A
= 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Source Current
Maximum Pulsed Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= -0.42
(Note 2)
-0.8
-0.42
-10
-1.2
A
A
V
P
D
(
t
) =
T
J
−T
A
R
θJA
(t)
=
T
J
−T
A
R
θJC
+R
θCA
(t)
=
I
2
(
t
) ×
R
DS(ON)@T
J
D
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250
o
C/W when mounted on a 0.02 in
2
pad of 2oz copper.
b. 270
o
C/W when mounted on a 0.001 in
2
pad of 2oz copper.
1a
1b
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS352AP Rev.D
Typical Electrical Characteristics
-5
I
D
, DRAIN-SOURCE CURRENT (A)
1.6
DRAIN-SOURCE ON-RESISTANCE
V
GS
= -10V
-7.0
-6.0
-5.5
R
DS(on)
, NORMALIZED
V
GS
= -3.5 V
1.4
1.2
1
0.8
0.6
0.4
-4
-5.0
-4.5
-4.0
-4.0
-4.5
-5.0
-5.5
-6.0
-7.0
-10
-3
-2
-3.5
-1
-3.0
0
-1
V
DS
0
-2
-3
-4
-5
0
-1
, DRAIN-SOURCE VOLTAGE (V)
-2
-3
I
D
, DRAIN CURRENT (A)
-4
-5
Figure 1. On-Region Characteristics
.
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
.
1.6
1.6
I
D
= -0.9A
R
DS(on)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE
1.4
V
GS
= -4.5V
1.4
1.2
1
0.8
0.6
0.4
TJ = 125°C
25°C
R
DS(ON)
, NORMALIZED
1.2
1
-55°C
0.8
V
GS
= -4.5V
0.2
0
-1
-2
I
D
, DRAIN CURRENT (A)
-3
-4
0.6
-50
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation
with Drain Current and Temperature
.
V
DS
= -10V
-3.2
T = -55°C
J
25
125
GATE-SOURCE THRESHOLD VOLTAGE
-4
1.2
I , DRAIN CURRENT (A)
1.1
-2.4
1
-1.6
0.9
D
-0.8
0.8
-1
-2
-3
-4
-5
V
GS
, GATE TO SOURCE VOLTAGE (V)
-6
0.7
-50
-25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
Figure 5. Transfer Characteristics.
Figure 6. Gate Threshold Variation
with Temperature
.
NDS352AP Rev.C
Typical Electrical Characteristics
(continued)
1.1
4
DRAIN-SOURCE BREAKDOWN VOLTAGE
V
GS
= 0V
-I , REVERSE DRAIN CURRENT (A)
I
D
= -250µA
1
1.08
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
T J = 125°C
0.1
BV
DSS
, NORMALIZED
25°C
-55°C
0.01
0.001
-25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
S
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
-V
SD
, BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 7. Breakdown Voltage Variation with
Temperature
.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
.
400
10
, GATE-SOURCE VOLTAGE (V)
300
200
I
D
= -0.9A
8
V
DS
= -5V
-10
-15
Ciss
CAPACITANCE (pF)
100
Coss
6
4
50
Crss
f = 1 MHz
V
GS
= 0 V
2
30
20
0 .1
-V
0 .2
0 .5
1
2
5
10
-V
, DRAIN TO SOURCE VOLTAGE (V)
DS
20
30
GS
0
0
1
Q
g
2
3
4
5
, GATE CHARGE (nC)
Figure 9. Capacitance Characteristics
.
Figure 10. Gate Charge Characteristics
.
V
DD
t
d(on)
t
on
t
r
90%
t
off
t
d(off)
90%
t
f
V
IN
D
R
L
V
OUT
V
OUT
10%
V
GS
R
GEN
10%
90%
G
DUT
S
V
IN
10%
50%
50%
PULSE WIDTH
INVERTED
Figure 11. Switching Test Circuit
.
Figure 12. Switching Waveforms
.
NDS352Ap Rev.C
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