FemtoClock
®
NG QUAD Universal
Frequency Translator
General Description
The IDT8T49N445I is a quad PLL with FemtoClock® NG technology.
The IDT8T49N445I integrates low phase noise Frequency
Translation / Synthesizer and jitter attenuation. It includes alarm and
monitoring functions suitable for networking and communications
applications. The device has four fully independent PLLs, each PLL
is able to generate any output frequency in the 0.98MHz - 312.5MHz
range and most output frequencies in the 312.5MHz - 1,300MHz
range (see Table 3 for details). A wide range of input reference
clocks may be used as the source for the output frequency.
Each PLL of IDT8T49N445I has three operating modes to support a
very broad spectrum of applications:
1) Frequency Synthesizer
IDT8T49N445I
DATA SHEET
Features
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Fourth generation FemtoClock® NG technology
Four fully independent PLLs
Universal Frequency Translator™ Frequency Synthesizer and
Jitter attenuator
Output is programmable as LVPECL or LVDS
Programmable output frequency: 0.98MHz up to 1,300MHz
Differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz (Low-Bandwidth mode)
Input frequency range: 16kHz - 710MHz (High-Bandwidth mode)
REFCLK frequency range: 16MHz - 40MHz
Input clock monitor on each PLL will smoothly switch between
redundant input references
Operation reference frequency range: 16MHz - 40MHz
Input clock monitor and alarm
Factory-set register configuration for power-up default state
Power-up default configuration
Configuration customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 161.1328125MHz, using 40MHz REFCLK
(12kHz - 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz, using 40MHz REFCLK
(12kHz - 20MHz): 333fs (typical), synthesizer Mode (integer FB)
Full 2.5V supply mode
-40°C to 85°C ambient operating temperature
10mm X 10mm CABGA
Lead-free (RoHS 6) packaging
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Synthesizes output frequencies from an external reference
clock REFCLK.
Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external reference clock REFCLK
to provide significant jitter attenuation.
2) High-Bandwidth Frequency Translator
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3) Low-Bandwidth Frequency Translator
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Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by the customer and are programmed
by IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured.
IDT8T49N445AASGI REVISION A JUNE 28, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8T49N445I Data Sheet
FEMTOCLOCK
®
NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
Complete Block Diagram
IDT8T49N445AASGI REVISION A JUNE 28, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8T49N445I Data Sheet
FEMTOCLOCK
®
NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
Pin Description and Pin Characteristic Tables
Table 1. Pin Description Table
Number
E5
C2
D2
B7
B6
G8
F8
H3
H4
B1, A2
A9, B9
J9, J8
J1, H1
A4, A5
D9, E9
J6, J5
F1, E1
E2
C5
E8
H5
G6
G5
C1
C4
B5
A7
D5
Name
REFCLK
CLKA
nCLKA
CLKB
nCLKB
CLKC
nCLKC
CLKD
nCLKD
QA, nQA
QB, nQB
QC, nQC
QD, nQD
LF0A, LF1A
LF0B, LF1B
LF0C, LF1C
LF0D, LF1D
LOCKA
LOCKB
LOCKC
LOCKD
SDATA
SCLK
V
CCA_A
V
CCO_A
V
CC_A
V
CCA_B
V
CCO_B
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Analog I/O
Analog I/O
Analog I/O
Analog I/O
Output
Output
Output
Output
I/O
Input
Power
Power
Power
Power
Power
Pullup
Pullup
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Reference clock for device operation. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating (set by the
internal pullup and pulldown resistors).
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
Loop filter connection node pins. LF0A is the output, LF1A is the input.
Loop filter connection node pins. LF0B is the output, LF1B is the input.
Loop filter connection node pins. LF0C is the output, LF1C is the input.
Loop filter connection node pins. LF0D is the output, LF1D is the input.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
I
2
C Data Input/Output. Open drain. LVCMOS/LVTTL interface levels.
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
Analog power supply for PLLA.
Output power supply for PLLA.
Core power supply for PLLA.
Analog power supply for PLLB.
Output power supply for PLLB.
3
©2013 Integrated Device Technology, Inc.
IDT8T49N445AASGI REVISION A JUNE 28, 2013
IDT8T49N445I Data Sheet
FEMTOCLOCK
®
NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
Table 1. Pin Description Table
Number
D7
E7
G9
F5
E3
J3
F3
A3, B2, B3
A8, B8, C9
H8, H9, J7
G1, H2, J2
A6, B4, C3,
C6, C7, D1,
D3, D4, D6,
D8, F2, F4,
F6, F7, F9,
G3, G4, G7,
E6
E4
C8
H7
G2
Name
V
CC_B
V
CCA_C
V
CCO_C
V
CC_C
V
CCA_D
V
CCO_D
V
CC_D
V
EE_A
V
EE_B
V
EE_C
V
EE_D
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
Description
Core power supply for PLLB.
Analog power supply for PLLC.
Output power supply for PLLC.
Core power supply for PLLC.
Analog power supply for PLLD.
Output power supply for PLLD.
Core power supply for PLLD.
Negative supply for PLLA.
Negative supply for PLLB.
Negative supply for PLLC.
Negative supply for PLLD.
nc
Unused
No connect. These pins are to be left unconnected.
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Input
Input
Input
Input
Input
Reserved, connect to V
EE.
Reserved, connect to V
EE.
Reserved, connect to V
EE.
Reserved, connect to V
EE.
Reserved, connect to V
EE.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Input Pulldown
Resistor
Input Pullup
Resistor
REFCLK
SDATA, SCLK
Test Conditions
Minimum
Typical
3.5
51
51
12.5
12.5
Maximum
Units
pF
k
k
k
k
IDT8T49N445AASGI REVISION A JUNE 28, 2013
4
©2013 Integrated Device Technology, Inc.
IDT8T49N445I Data Sheet
FEMTOCLOCK
®
NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
Pin Assignment
J
QD
GND
VCCO_D
nc
LF1C
LF0C
GND
nQC
QC
H
nQD
GND
CLKD
nCLKD
LOCKD
nc
RSVD
GND
GND
G
GND
RSVD
nc
nc
SCLK
SDATA
nc
CLKC
VCCO_C
F
LF0D
nc
VCC_D
nc
VCC_C
nc
nc
nCLKC
nC
E
LFID
LOCKA
VCCA_D
RSVD
REFCLK
nc
VCCA_C
LOCKC
LF1B
D
nc
nCLKA
nc
nc
VCCO_B
nc
VCC_B
nc
LF0B
C
VCCA_A
CLKA
nc
VCCO_A
LOCKB
nc
nc
RSVD
GND
B
QA
GND
GND
nc
VCC_A
nCLKB
CLKB
GND
nQB
A
nQA
GND
LF0A
LF1A
nc
VCCA_B
GND
QB
1
2
3
4
5
6
7
8
9
IDT8T49N445I Pin Map
80-Ball Lead
10mm x 10mm x1mm package body
CABGA Package
(bottom view)
IDT8T49N445AASGI REVISION A JUNE 28, 2013
5
©2013 Integrated Device Technology, Inc.
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