Low Skew, 1-to-2 Differential-to-LVDS
Fanout Buffer
Data Sheet
85411I
G
ENERAL
D
ESCRIPTION
The 85411I is a low skew, high performance 1-to-2 Differential-
to-LVDS Fanout Buffer and a member of the family of High
Performance Clock Solutions from IDT. The CLK, nCLK pair
can accept most standard differential input levels.The 85411I is
characterized to operate from a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make the 85411I ideal
for those clock distribution applications demanding well defined
performance and repeatability.
F
EATURES
•
Two differential LVDS outputs
•
One differential CLK, nCLK clock input
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 650MHz
•
Translates any single ended input signal to
LVDS levels with resistor bias on nCLK input
•
Output skew: 25ps (maximum)
•
Part-to-part skew: 300ps (maximum)
•
Additive phase jitter, RMS: 0.05ps (typical)
•
Propagation delay: 2.5ns (maximum)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead free (RoHS 6) package
B
LOCK
D
IAGRAM
CLK
nCLK
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
V
DD
CLK
nCLK
GND
85411I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B January 20, 2016
85411I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
GND
nCLK
CLK
V
DD
Output
Output
Power
Input
Input
Power
Pullup
Type
Description
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply ground.
Pulldown Inverting differential clock input.
Non-inverting differential clock input.
Positive supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
©2016 Integrated Device Technology, Inc
2
Revision B January 20, 2016
85411I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
112.7°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.97
Typical
3.3
Maximum
3.63
50
Units
V
mA
T
ABLE
3B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.63V
V
DD
= V
IN
= 3.63V
V
DD
= 3.63, V
IN
= 0V
V
DD
= 3.63V, V
IN
= 0V
-150
-5
0.15
0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Test Conditions
Minimum
247
1.325
-20
Typical
325
0
1.45
5
±1
-3.5
-3.5
Maximum
454
50
1.575
50
+20
-5
-5
Units
mV
mV
V
mV
µA
mA
mA
V
OS
Δ
V
OS
I
OFF
I
OSD
I
OS
©2016 Integrated Device Technology, Inc
3
Revision B January 20, 2016
85411I Data Sheet
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 3.3V±10% T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
(12kHz to 20MHz)
20% to 80% @ 50MHz
f > 500MHz
f
≤
500MHz
150
46
48
0.05
350
54
52
1.5
Test Conditions
Minimum
Typical
Maximum
650
2.5
25
300
Units
MHz
ns
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
All parameters measured at ƒ
≤
650MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
4
Revision B January 20, 2016
85411I Data Sheet
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
Input/Output Additive Phase Jit-
ter
@ 200MHz (12kHz to 20MHz)
= 0.05ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
500M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what
is shown, but can actually be lower. The phase noise is dependent
on the input source and measurement equipment.
©2016 Integrated Device Technology, Inc
5
Revision B January 20, 2016
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