Am29F800B
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
21504
Revision
E
Amendment
5
Issue Date
November 2, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■
Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F800 device
■
High performance
— Access times as fast as 55 ns
■
Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
— Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Top or bottom boot block configurations
available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 1,000,000 program/erase cycles per
sector guaranteed
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package option
— 48-pin TSOP
— 44-pin SO
— 48-ball FBGA
— Known Good Die (KGD)
(see publication number 21631)
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21504
Rev:
E
Amendment:
5
Issue Date:
November 2, 2006
DATA SHEET
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO, 48-pin
TSOP, and 48-ball FBGA packages. The device is also
available in Known Good Die (KGD) form. For more
information, refer to publication number 21631. The
word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device
is designed to be programmed in-system with the stan-
dard system 5.0 volt V
CC
supply. A 12.0 V V
PP
is not
required for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29F800, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the
standby
mode.
Power consumption is greatly reduced in
this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
Am29F800B
21504E5 November 2, 2006
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .................... 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29F800B Device Bus Operations ..................................9
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
TTL/NMOS Compatible .......................................................... 24
CMOS Compatible .................................................................. 25
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Test Setup....................................................................... 26
Table 7. Test Specifications ........................................................... 26
Key to Switching Waveforms. . . . . . . . . . . . . . . . 26
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Read Operations .................................................................... 27
Figure 9. Read Operations Timings ............................................... 27
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 10
Table 2. Am29F800BT Top Boot Block Sector Address Table .......11
Table 3. Am29F800BB Bottom Boot Block Sector Address Table ..12
Hardware Reset (RESET#) .................................................... 28
Figure 10. RESET# Timings .......................................................... 28
Word/Byte Configuration (BYTE#) ........................................ 29
Figure 11. BYTE# Timings for Read Operations............................ 29
Figure 12. BYTE# Timings for Write Operations............................ 29
Erase/Program Operations ..................................................... 30
Figure 13. Program Operation Timings..........................................
Figure 14. Chip/Sector Erase Operation Timings ..........................
Figure 15. Data# Polling Timings (During Embedded Algorithms).
Figure 16. Toggle Bit Timings (During Embedded Algorithms)......
Figure 17. DQ2 vs. DQ6.................................................................
31
32
33
33
34
Autoselect Mode ..................................................................... 12
Table 4. Am29F800B Autoselect Codes (High Voltage Method) ....13
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Figure 1. Temporary Sector Unprotect Operation........................... 13
Temporary Sector Unprotect .................................................. 34
Figure 18. Temporary Sector Unprotect Timing Diagram .............. 34
Figure 19. Alternate CE# Controlled Write Operation Timings ...... 36
Hardware Data Protection ...................................................... 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data ................................................................ 14
Reset Command ..................................................................... 14
Autoselect Command Sequence ............................................ 15
Word/Byte Program Command Sequence ............................. 15
Figure 2. Program Operation .......................................................... 15
Chip Erase Command Sequence ........................................... 15
Sector Erase Command Sequence ........................................ 16
Erase Suspend/Erase Resume Commands ........................... 16
Figure 3. Erase Operation............................................................... 17
Command Definitions ............................................................. 18
Table 5. Am29F800B Command Definitions ...................................18
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19
DQ7: Data# Polling ................................................................. 19
Figure 4. Data# Polling Algorithm ................................................... 19
RY/BY#: Ready/Busy# ........................................................... 20
DQ6: Toggle Bit I .................................................................... 20
DQ2: Toggle Bit II ................................................................... 20
Reading Toggle Bits DQ6/DQ2 .............................................. 20
DQ5: Exceeded Timing Limits ................................................ 21
DQ3: Sector Erase Timer ....................................................... 21
Figure 5. Toggle Bit Algorithm......................................................... 21
Table 6. Write Operation Status ......................................................22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 23
Figure 6. Maximum Negative Overshoot Waveform ....................... 23
Figure 7. Maximum Positive Overshoot Waveform......................... 23
Erase and Programming Performance . . . . . . . 37
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 37
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 37
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38
SO 044—44-Pin Small Outline Package ................................ 38
TS 048—48-Pin Standard Pinout Thin Small
Outline Package (TSOP) ........................................................ 39
FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm
package .................................................................................. 40
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision A (August 1997) ....................................................... 41
Revision B (October 1997) ..................................................... 41
Revision C (January 1998) ..................................................... 41
Revision C+1 (April 1998) ....................................................... 41
Revision C+2 (April 1998) ....................................................... 41
Revision D (January 1999) ..................................................... 42
Revision D+1 (March 23, 1999) .............................................. 42
Revision D+2 (July 2, 1999) ................................................... 42
Revision E (November 16, 1999) ............................................ 42
Revision E+1 (August 4, 2000) ............................................... 42
Revision E+2 (June 4, 2004) .................................................. 42
Revision E3 (December 22, 2005) .......................................... 42
Revision E4 (May 19, 2006) ................................................... 42
Revision E5 (November 2, 2006) ............................................ 42
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 23
November 2, 2006 21504E5
Am29F800B
3
FPGA/CPLD
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