Micrel, Inc.
3.3V 28Mbps-2.7Gbps AnyRate
®
CLOCK AND DATA RECOVERY WITH
INTEGRATED CLOCK MULTIPLIER UNIT
DESCRIPTION
SY87721L
SY87721L
FEATURES
s
Recovers any data and clock from 28Mbps to
2.7Gbps
• OC-1, OC-3, OC-12, OC-48, ATM
• Gigabit Ethernet, Fast Ethernet
• Fibre Channel, 2x Fibre Channel
• P1394, Infiniband
• SMPTE-259, SMPTE-292
• Proprietary optical transport
s
Integrated clock multiplier unit with low jitter
generation
s
Complies with Bellcore, ITU/CCITT and ANSI
specifications
s
Selectable mux for pass through; avoids jitter
accumulation when switching through backplanes
s
Available in 64-Pin EPAD-TQFP package
The SY87721L is a complete Clock Recovery and Data
retiming integrated circuit for data rates from 28Mbps up to
2.7Gbps NRZ including SONET FEC data rates. Included
in the device, is a fully integrated Clock Multiplier Unit (CMU)
that is capable of generating frequencies that cover the
same data rate range as the CDR. The device is ideally
suited for SONET/SDH/ATM, Fibre Channel, and Gigabit
Ethernet applications, as well as other high-speed data
transmission applications.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming data
stream. The VCO center frequency is controlled by the
reference clock frequency and the selected divide ratio.
On-chip clock generation is performed through the use of a
frequency multiplier PLL with a byte rate or code group rate
source as reference.
SIMPLIFIED BLOCK DIAGRAM
SY87721L
AnyRate
Data In
2
CDR
AnyRate
Data Out
2
2
Recovered
Clock
Reference
Clock
2
CMU
2
Transmit
Clock
APPLICATIONS
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SONET/SDH/ATM-based transmission systems,
modules, and test equipment
s
Transponders and section repeaters
s
Multiplexers: access, add drop (ADM), and terminal (TM)
s
Terabit routers and broadband cross-connects
s
Fiber optic test equipment
AnyRate is a registered trademark of Micrel, Inc.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: C
Amendment: /0
Issue Date: October 2005
Micrel, Inc.
SY87721L
PIN NAMES
INPUTS
BRDMX [BRD Mux]
– PECL Input
This signal indicates what data appears at the BRD±
output. When logic HIGH, BRD± is a direct copy of what
appears at RDOUTC±. When logic low, BRD± is a copy of
what appears at RDIN±. Unlike RDOUTC±, BRD± conveys
valid data even when ENPECL is logic LOW. Please refer
to Table 1.
BRDMX (Input)
0
1
BRD
±
(Output)
RDIN±
RDOUTC±
Table 1. BRDMX Truth Table
DIVSEL1, ..., DIVSEL3 [Divider Select]
– TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 4. Please note that the divide by 32
selection, “011”, is only available for use when FREQSEL
are set to “000.”
DIVSEL1
0
0
0
0
1
1
1
1
DIVSEL2
0
0
1
1
0
0
1
1
DIVSEL3
0
1
0
1
0
1
0
1
REFCLK
Multiplier
1
2
4
32
8
10
16
20
RDIN
±
[Serial Data Input]
– Differential PECL Input
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75KΩ resistor tied to V
CC
.
REFCLK
±
[Reference Clock]
– Differential PECL Input
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 340MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75KΩ resistor tied to V
CC
.
CD [Carrier Detect]
– PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDOUT output will be internally forced to a
constant LOW, the Link Fault Indicator output LFIN forced
LOW, and the clock recovery PLL forced to lock onto the
synthesized clock frequency generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select]
– TTL Inputs
These inputs select the output clock frequency range via
either one of three PLLs, or a SONET/SDH specific PLL.
Only the selected PLL is enabled. All other PLLs are
disabled. Refer to Table 3 for more details.
FREQSEL1, ..., FREQSEL3 [Frequency Select]
– TTL Inputs
These inputs select the post divide ratio of the VCO.
Refer to Table 3 for more details.
Table 2
(1)
. Reference Clock Multiplier Truth Table
Note:
1. Some combinations of FREQSEL and DIVSEL result in undefined behavior.
Refer to Table 3 for more details.
CLKSEL [Clock Select]
– TTL Input
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs. Do not use for skew matching.
ENPECL [Enable ECL]
– TTL Input
This input, when HIGH (ENPECL = 1), enables the
differential PECL outputs TCLKE±, RDOUTE±, and RCLKE±.
It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,
RDOUTC–, and RCLKC– logic LOW.
When set LOW (ENPECL = 0), this signal enables the
differential CML outputs TCLKC±, RDOUTC±, and RCLKC±.
It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,
RDOUTE– and RCLKE– logic LOW.
ALRSEL [Auto Lock Range Select]
– TTL Input
This pin defines the frequency difference, and the
frequency difference hysteresis at which ‘in-lock’ and ‘out of
lock’ conditions are declared. Please refer to the “AC
Characteristics” for more details.
M9999-102405
hbwhelp@micrel.com or (408) 955-1690
5
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