MOSA ELECTRONICS
Features
•
•
•
•
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Complete DTMF receiver
Low power consumption
Adjustable guard time
Central Office Quality
CMOS, Single 5V operation
O
MS8870
DTMF Receiver
rdering Information
MS8870 : 18 PIN DIP PACKAGE
Description
The MS8870 is a complete DTMF receiver integrating
both the bandsplit filter and digital decoder functions,
fabricated in double poly technology and is pin and
function compatible with MITEL8870. The filter section
uses switched capacitor techniques for high and low group
filters; the decoder uses digital counting techniques to
detect and decode all 16 DTMF tone-pairs into a 4-bit code.
External component count is minimized by on chip
provision of a differential input amplifier, clock oscillator
and latched 3-state bus interface.
Figure 1. Functional Block Diagram
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1
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MOSA ELECTRONICS
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11-14
15
Name
IN +
IN -
GS
V
REF
IC
IC
OSC1
OSC2
Vss
TOE
Q1-Q4
StD
Description
MS8870
DTMF Receiver
16
ESt
17
St/GT
18
V
DD
Non-inverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection
of feedback resistor.
Reference voltage output, nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig.
2).
Internal connection. Must be tied to Vss.
Internal connection. Must be tied to Vss.
Clock input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit.
Negative power supply input.
3-state output enable (input). Logic high enables the outputs Q1-Q4 Internal pull up.
3-state data output. When enable by TOE, provide the code corresponding to the last
valid tone-pair received (see Fig. 5).
Delayed steering output. Presents a logic high when a received tone-pair has been
registered and the output latch updated; return to logic low when the voltage on St/GT
falls below V
TS
t.
Early steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
Steering input/guard time output (bi-directional). A voltage greater than V
TS
t detected
at St causes the device to register the detected tone pair and update the output latch. A
Voltage less than V
TS
t frees the device to accept a new tone pair. The GT output acts
to reset the external steering time-constant; its state is a function of ESt and the
voltage on St.
Positive power supply input.
Absolute Maximum Ratings
Parameter
1
2
3
4
5
6
Power supply voltage V
DD
-Vss
Voltage on any pin
Current at any pin
Operating temperature
Storage temperature
Package power dissipation
Min
Vss - 0.3
-40
-65
Max
6
V
DD
+ 0.3
10
+85
+150
1000
Units
V
V
mA
℃
℃
mW
－
2
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MOSA ELECTRONICS
DC Electrical Characteristics
Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S
U
P
P
L
Y
I
N
P
U
T
S
O
U
T
P
U
T
S
Operating supply voltage
Operating supply current
Power consumption
High level input
Low level input voltage
Input leakage current
Pull up (source) current
Input impedance (IN+, IN-)
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (
source
) current
V
R
ef output voltage
V
R
ef output resistance
I
DD
P
O
V
IH
V
IL
I
IH
/I
IL
I
SO
R
IN
V
TS
t
V
OL
V
OH
I
OL
I
OH
V
R
ef
R
OR
3.5
1.5
0.1
7.5
10
2.2
4.97
1
0.4
2.4
2.5
0.03
2.5
0.8
2.8
10
Sym
Min
4.75
Typ
5.0
3.0
15
Max
5.25
9.0
45
Units
V
mA
mW
V
V
µ
A
µ
A
M
Ω
V
V
V
mA
mA
V
K
Ω
MS8870
DTMF Receiver
Test Conditions
f = 3.58 MHz; V
DD
= 5V
V
IN
= Vss or V
DD
TOE (pin 10) = 0 V
@ 1 KHz
No load
No load
V
OUT
= 0.4V
V
OUT
= 4.6V
No load
Operating Characteristics
Gain Setting Amplifier
Characteristics
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Maximum capacitive load (GS)
Maximum resistive load (GS)
Common mode range
Notes :
Sym
I
IN
R
IN
Vos
PSRR
CMRR
A
VOL
fc
Vo
C
L
R
L
V
CM
Min
Typ
100
10
25
60
60
65
1.5
4.5
100
50
3.0
Max
Units
nA
M
Ω
mV
dB
dB
dB
MHz
Vpp
pF
K
Ω
Vpp
Vss
≤
Test Conditions
V
IN
≤
V
DD
1 KHz
-3.0V
≤
V
IN
≤
3.0V
R
L
≥
100K
Ω
to Vss
No Load
1. All voltages referenced to Vss unless otherwise noted.
2. Vcc = 5.0V, Vss = 0V, T
A
= 25
℃
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3
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MOSA ELECTRONICS
AC Electrical Characteristics *
Characteristics
S
I
G
N
A
L
C
O
N
D.
T
I
M
I
N
G
O
U
T
P
U
T
S
C
L
O
C
K
Valid input signal levels
(each tone of composite signal)
Positive twist accept
Negative twist accept
Freq. deviation accept
Freq. deviation reject
Third tone tolerance
Noise tolerance
Dial tone tolerance
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up ( Q to StD)
Propagation delay (TOE to Q
ENABLE)
Propagation delay (TOE to Q
DISABLE)
Crystal / clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
Sym
Min
-29
27.5
+1
883
Typ
Max
Units
dBm
mV
RMS
dBm
mV
RMS
dB
dB
Nom.
Nom.
dB
dB
dB
ms
ms
ms
ms
ms
ms
µ
s
µ
s
µ
s
ns
ns
3.5831
110
110
60
30
MHz
ns
ns
%
pF
MS8870
DTMF Receiver
Notes
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
2,3,6,9
2,3,6,9
2,3,5,9
2,3,5,9
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9,11
Refer to Fig. 3
Refer to Fig. 3
User adjustable
User adjustable
User adjustable
User adjustable
TOE = V
DD
TOE = V
DD
TOE = V
DD
RL = 10K
Ω
CL = 50 pF
RL = 10K
Ω
CL = 50 pF
Ext. clock
Ext. clock
Ext. clock
±
1.5%
±
2Hz
±
3.5%
10
10
t
DP
t
DA
t
REC
/t
REC
t
ID
t
DO
t
PQ
t
PStD
t
QStD
t
PTE
t
PTD
fc
t
LHCL
t
HLCL
DC
DL
C
LO
5
0.5
20
-16
-12
+22
11
4
14
8.5
40
40
20
8
12
3.4
50
300
3.5759
3.5795
11
40
50
* All voltages referenced to Vss unless otherwise noted. Vcc = 5.0V,
test circuit shown in Figure 2
Vss = 0V, T
A
= 25℃, Fc = 3.579545 MHz, using
NOTES
1. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms, tone pause = 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by
±
1.5%
±
2 Hz.
7. Bandwidth limited (3 KHz) Gaussian noise.
8. The precise dial tone frequencies are ( 350 Hz and 440 Hz)
±
2%.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
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4
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MOSA ELECTRONICS
MS8870
DTMF Receiver
NOTES :
R1, R2 = 100K 1%
R3 = 300K 1%
C1, C2 = 100nF 5%
X1 = 3.579545 MHz
Figure 2. Single Ended Input Configuration
Figure 3. Timing Diagram
EXPLANATION OF EVENTS
A ) Short tone bursts: detected. Tone duration is invalid.
B ) Tone #n is detected. Tone duration is valid. Decoded to outputs.
C ) End of Tone #n is detected and validated.
D ) 3-State outputs disable ( high impedance).
E ) Tone #n + 1 is detected. Tone duration is valid. Decoded to outputs.
F ) Tristate outputs are enabled. Acceptable drop out of Tone #n + 1 does not register at outputs.
G ) End of Tone #n + 1 is detected and validated.
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5
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传感器
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