Preliminary
FM1112
Nonvolatile 3V Quad State Saver
Features
Nonvolatile State Saver
•
Logic States Retained in Absence of Power
•
Outputs Automatically Restored at Power-up
•
Unlimited Number of State Changes
•
Max t
PD
50ns at 2.7V
•
Max Frequency 1 MHz
Low Power Operation
•
Supply voltage of 2.7V to 3.6V
•
10
µA
Standby Current
Industry Standard Configuration
•
Industrial Temperature -40° C to +85° C
•
16-pin “Green”/RoHS QFN Package
Overview
The FM1112 is an innovative FRAM-based device
that stores inputs like conventional logic and retains
the stored state in the absence of power. This product
solves three basic problems in an elegant fashion.
First, it provides continuous access to nonvolatile
system settings without performing a memory read
operation or using dedicated processor I/O pins.
Second, it allows the storage of signals that may
change frequently and possibly without notice. Third,
it allows the nonvolatile storage of a system setting
without the system overhead and extra pins of a serial
memory.
Functionally, the inputs are stored and passed to the
output on the rising edge of the clock CLK. This
unique product serves a variety of applications. Here
are a few applications:
!
!
!
!
!
Control relays or valves with automatic setting
on power-up without processor intervention
Interface to soft/momentary front-panel switch
and indicator lamp. Capture switch settings and
drive LEDs without processor intervention
Replaces jumpers & control signal routing
Initialize state of I/O card signals
Eliminate the overhead of serial memory for
systems needing only a bit of data
Pin Configuration
VDD
NC
NC
EN
VDD
D0
Q0
D1
15
1
2
3
Q2
11
D2
D3
CLK
VSS
Q1
7
4
VSS
Top View
Pin Names
D
N
Q
N
EN
CLK
VDD
VSS
Function
Data In
Data Out
Enable
Clock
Supply Voltage
Ground
Ordering Information
FM1112-QG
Quad State Saver,
16-pin “Green”/RoHS QFN
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.0
Aug. 2007
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 8
Q3
FM1112 NV Quad State Saver
Block Diagram and Truth Table
INPUTS
CLK
↑
↑
H or L
X
OUTPUT
Qn
L
H
Q
0
Hi-Z
D
N
CLK
NV
State
Saver
Q
N
EN
EN
H
H
H
L
L
H
X
↑
Q
0
Dn
L
H
X
X
Low voltage level
High voltage level
Don’t Care
CLK rising edge
Previous output state before CLK
↑
Pin Descriptions
Pin Name
D(3:0)
Q(3:0)
CLK
EN
VDD
VSS
I/O
I
O
I
I
Supply
Supply
Description
Data inputs
Data outputs
Clock: On a rising edge of CLK, the D
N
inputs are transferred to the Q
N
outputs. While
CLK is high or low, the Q
N
outputs do not change regardless of the state of the data
inputs. See truth table.
Enable. This active-high input enables the device. When low, inputs are ignored and
updates to the nonvolatile cells are prevented. When high, the device operates
normally.
Power Supply (2.7V to 3.6V)
Ground
Rev. 1.0
Aug. 2007
Page 2 of 8
FM1112 NV Quad State Saver
Description
Nonvolatile storage applied to logic is a
revolutionary concept. The FM1112 simplifies the
design of system control functions. This product is
unique because it remembers the stored output
values in the absence of power. Any change in the
latched state is automatically written to a nonvolatile
ferroelectric latch. This function is possible due to
the fast write time and extremely high write
endurance of the underlying ferroelectric memory
technology.
Use of Enable Pin
The FM1112 has an enable pin that is intended to be
used in conjunction with a system reset. An active-
low reset may be tied directly to the EN pin. At
power-up, /RESET will be held low for some time
during which the data input and CLK pins will be
ignored. Once the system comes out of reset and EN
goes high, the outputs Q
N
drive to the state that were
previously latched and the device operates normally.
When the EN pin is low, the outputs Q
N
are tri-
stated.
The enable pin may be tied to V
DD
since the device
integrates a power management circuit that monitors
the V
DD
level during power cycles.
Rev. 1.0
Aug. 2007
Page 3 of 8
FM1112 NV Quad State Saver
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
V
DD
Power Supply Voltage with respect to V
SS
V
IN
Voltage on any signal pin with respect to V
SS
T
STG
T
LEAD
Storage temperature
Lead temperature (Soldering, 10 seconds)
Ratings
-1.0V to +5.0V
-1.0V to +5.0V
and V
IN
< V
DD
+1.0V
-55°C to + 125°C
300° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions
(
T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
DD
Power Supply Voltage
2.7
-
3.6
V
I
SB
Standby Current
-
10
µ
A
1
C
PD
Power Dissipation Capacitance
-
330
pF
2
I
LI
Input Leakage Current
3
±1
µA
I
LO
Output Leakage Current
3
±1
µA
V
IL
Input Low Voltage
-0.3
0.3 V
DD
V
V
IH
Input High Voltage
0.7 V
DD
V
DD
+ 0.3
V
V
OH
Output High Voltage
@
I
OH
= -1 mA
V
DD
– 0.5
-
V
V
OL
Output Low Voltage
V
0.4
-
@
I
OL
= 1 mA (V
DD
=2.7V)
V
0.8
-
@
I
OL
= 10 mA (V
DD
=2.7V)
V
HYS
Input Hysteresis (CLK, D
N
, EN)
0.05 V
DD
V
4
Notes
1.
CLK = V
SS
, all other inputs at V
DD
or V
SS
.
2.
To calculate device power dissipation, P
D
= C
PD
*V
DD2
*f
i
+ C
L
*V
DD2
*f
o
, where f
i
is the input clk freq, f
o
is the output freq,
3.
4.
and C
L
is the output load capacitance. Active current I
DD
may be calculated as I
DD
= C
PD
*V
DD
*f
i
, assuming outputs are
floating.
V
IN
or V
OUT
= V
SS
to V
DD
.
This parameter is characterized but not tested.
Rev. 1.0
Aug. 2007
Page 4 of 8
FM1112 NV Quad State Saver
AC Parameters
(T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V, C
L
= 30 pF unless otherwise specified)
Symbol
Parameter
Min
Max
f
MAX
Maximum Clock Frequency
1
t
LOW
CLK Low Period
0.3
t
HIGH
CLK High Period
0.3
t
PD
Propagation delay CLK to Q
N
50
t
HZ
EN Low to Q
N
Hi-Z
25
t
R
Input Rise Time
100
t
F
Input Fall Time
100
t
DS
Data (D
N
) Setup Time to CLK
↑
5
t
DH
Data (D
N
) Hold Time after CLK
↑
10
t
EHD
EN Hold Time (EN High after CLK
↑
)
0
t
EH
EN High Time
5
t
EL
EN Low Time
2
Notes
1.
This parameter is characterized but not tested.
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
Notes
1
1
1
Power Cycling and Data Retention
(T
A
= -40° C to + 85° C, V
DD
= 2.7V to 3.6V, unless otherwise specified)
Symbol
Parameter
Min
Max
Units
Nonvolatile Data Retention Time
45
-
years
t
VDR
V
DD
Rise Time
25
-
µs/V
t
VDF
V
DD
Fall Time
50
-
µs/V
t
RES
EN High to Q
N
Restore Time
-
0.5
µs
t
PDS
EN Low to Power Down Time
1
-
µs
t
EHFC
EN High to First Clock (CLK
↑
) after Power Up
4
-
µs
Notes
1.
2.
3.
Notes
1
1
2
3
Slope measured at any point on V
DD
waveform.
After power up, when EN goes high the nonvolatile latches are read and the values restored to the outputs Q
N
.
After power up, this is the minimum time required before a state change operation may occur. EN and V
DD
may be
coincident at power up, and in this case t
EHFC
time is referenced to V
DD
(min) and CLK
↑
.
Capacitance
(T
A
= 25° C , f=1.0 MHz, V
DD
= 3.3V)
Symbol
Parameter
C
I
Input Capacitance
Notes
1.
This parameter is characterized but not tested.
Min
-
Max
14
Units
pF
Notes
1
Rev. 1.0
Aug. 2007
Page 5 of 8
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