Preliminary
FM3130
Integrated RTC/Alarm and 64Kb FRAM
Features
High Integration Device Replaces Multiple Parts
•
Serial Nonvolatile Memory
•
Real-time Clock (RTC) with Alarm
•
Clock Output (Programmable frequency)
64Kb Ferroelectric Nonvolatile RAM
•
Internally Organized as 8Kx8
•
Unlimited Read/Write Endurance
•
10 year Data Retention
•
NoDelay™ Writes
Fast Two-wire Serial Interface
•
Up to 1 MHz Maximum Bus Frequency
•
Supports Legacy Timing for 100 kHz & 400 kHz
•
RTC & FRAM Controlled via 2-wire Interface
Real-time Clock/Calendar
•
Backup Current under 1
µA
•
Seconds through Centuries in BCD format
•
Tracks Leap Years through 2099
•
Uses Standard 32.768 kHz Crystal (12.5pF)
•
Software Calibration
•
Supports Battery or Capacitor Backup
Easy to Use Configurations
•
Operates from 2.7 to 3.6V
•
8-pin “green” SOIC (-G) and TDFN (-DG)
•
Low Operating Current
•
Industrial Temperature -40°C to +85°C
Description
The FM3130 integrates a real-time clock (RTC) and
FRAM nonvolatile memory. The device operates
from 2.7 to 3.6V.
The FM3130 provides nonvolatile FRAM which
features fast write speed and unlimited endurance.
This allows the memory to serve as extra RAM for
the system microcontroller or conventional
nonvolatile storage. This memory is truly nonvolatile
rather than battery backed.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
calibration mode that allows software adjustment of
timekeeping accuracy.
Pin Configuration
X1
X2
VBAK
VSS
1
2
3
4
8
7
6
5
VDD
ACS
SCL
SDA
X1
X2
VBAK
VSS
1
2
3
4
Top View
8
7
6
5
VDD
ACS
SCL
SDA
Pin Name
X1, X2
ACS
SDA
SCL
VBAK
VDD
VSS
Function
Crystal Connections
Alarm/Calibration/SqWave
Serial Data
Serial Clock
Battery-Backup Supply
Supply Voltage
Ground
Ordering Information
FM3130-G
FM3130-DG
“Green” 8-pin SOIC
“Green” 8-pin TDFN
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 22
Rev. 1.0
Sept. 2006
FM3130 Integrated RTC/Alarm with 64Kb FRAM
SCL
SDA
2-Wire
Interface
LockOut
FRAM
Array
Special
Function
Registers
RTC Cal.
RTC Registers
X1
RTC
X2
V
SW
VDD
-
+
Alarm
Alarm
512Hz/SQW
Switched Power
VBAK
ACS
Nonvolatile
Battery Backed
Figure 1. Block Diagram
Pin Descriptions
Pin Name
X1, X2
ACS
Type
I/O
Output
Pin Description
32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1
and a DC mid-level to X2 (see Crystal Type section for suggestions).
Alarm/Calibration/SquareWave: This is an open-drain output that requires an external
pullup resistor. The alarm, calibration, and square wave functions all share this output.
In Alarm mode, this pin acts as the active-low alarm output. In Calibration mode, a 512
Hz square-wave is driven out. In SquareWave mode, the user may select a frequency of
1, 512, 4096, or 32768 Hz to be used as a continuous output. Refer to
Table 3. Control
Bit Settings for ACS Pin
to determine the bit settings for each mode.
Serial Data & Address: This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR’d with other devices on the two-wire bus. The
input buffer incorporates a Schmitt trigger for noise immunity and the output driver
includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock line for the two-wire interface. Data is clocked out of the
part on the falling edge, and data into the device on the rising edge. The SCL input also
incorporates a Schmitt trigger input for noise immunity.
Backup supply voltage: A 3V battery or a large value capacitor. If no backup supply is
used, this pin should be tied to V
SS
.
Supply Voltage.
Ground
SDA
I/O
SCL
VBAK
VDD
VSS
Input
Supply
Supply
Supply
Rev. 1.0
Sept. 2006
Page 2 of 22
FM3130 Integrated RTC/Alarm with 64Kb FRAM
Overview
The FM3130 device combines a serial nonvolatile
RAM with a real-time clock (RTC) and alarm. These
complementary but distinct functions share a
common interface in a single package. Although
monolithic, the product is organized as two logical
devices, the FRAM memory and the RTC/alarm.
From the system perspective, they appear to be two
separate devices with unique IDs on the serial bus.
The memory is organized as a stand-alone 2-wire
nonvolatile memory with a standard device ID value.
The real-time clock and alarm are accessed with a
separate 2-wire device ID. This allows clock/calendar
data to be read while maintaining the most recently
used memory address. The clock and alarm are
controlled by 15 special function registers. The
registers are maintained by the power source on the
VBAK pin, allowing them to operate from battery or
backup capacitor power when V
DD
drops below a set
threshold. Each functional block is described below.
Real-Time Clock Operation
The real-time clock (RTC) is a timekeeping device
that can be battery or capacitor backed for
permanently-powered operation. It offers a software
calibration feature that allows high accuracy.
The RTC consists of an oscillator, clock divider, and
a register system for user access. It divides down the
32.768 kHz time-base and provides a minimum
resolution of seconds (1Hz). Static registers provide
the user with read/write access to the time values. It
includes registers for seconds, minutes, hours, day-
of-the-week, date, months, and years. A block
diagram (Figure 2) illustrates the RTC function.
The user registers are synchronized with the
timekeeper core using R and W bits in register 00h
described below. Changing the R bit from 0 to 1
transfers timekeeping information from the core into
holding registers that can be read by the user. If a
timekeeper update is pending when R is set, then the
core will be updated prior to loading the user
registers. The registers are frozen and will not be
updated again until the R bit is cleared to ‘0’. R is
used to read the time.
Setting the W bit to ‘1’ locks the user registers.
Clearing it to a ‘0’ causes the values in the user
registers to be loaded into the timekeeper core. W is
used for writing new time values. Users should be
certain not to load invalid values, such as FFh, to the
timekeeping registers. Updates to the timekeeping
core occur continuously except when locked. All
timekeeping registers must be initialized at the first
powerup or when the LB bit is set. See the
description of the LB bit on page 11.
Backup Power
The real-time clock/calendar is intended to be
permanently powered. When the primary system
power fails, the voltage on the V
DD
pin will drop.
When V
DD
is less than V
SW
, the RTC will switch to
the backup power supply on V
BAK
. The clock
operates at extremely low current in order to
maximize battery or capacitor life. However, an
advantage of combining a clock function with FRAM
memory is that data is not lost regardless of the
backup power source.
If a battery is applied without a V
DD
power supply,
the device has been designed to ensure the I
BAK
current does not exceed the 1µA maximum limit.
Trickle Charger
To facilitate capacitor backup the V
BAK
pin can
optionally provide a trickle charge current. When the
Memory Operation
The FM3130 integrates a 64Kb FRAM. The memory
is organized in bytes, 8192 addresses of 8 bits each.
The memory is based on FRAM technology.
Therefore it can be treated as RAM and is read or
written at the speed of the two-wire bus with no
delays for write operations. It also offers effectively
unlimited write endurance unlike other nonvolatile
memory technologies. The two-wire interface
protocol is described further on page 12.
The memory array can be write-protected by
software. Two bits (WP0, WP1) in register 0Eh
control the protection setting as shown in the
following table. Based on the setting, the protected
addresses cannot be written and the 2-wire interface
will not acknowledge any data to protected addresses.
The special function registers containing these bits
are described in detail below.
Table 1. FRAM Write-Protect
Write-Protect Range
WP1
None
0
Bottom 1/4
0
Bottom 1/2
1
Full array
1
WP0
0
1
0
1
The WP bits are battery-backed. On a powerup
without a backup source, the WP bits are cleared to a
‘0’ state.
Rev. 1.0
Sept. 2006
Page 3 of 22
FM3130 Integrated RTC/Alarm with 64Kb FRAM
VBC bit (register 0Eh, bit 2) is set to a ‘1’, the V
BAK
pin will source approximately 80 µA until V
BAK
reaches V
DD
. This charges the capacitor to V
DD
without an external diode and resistor charger.
There is a Fast Charge mode which is enabled by the
FC bit (register 0Eh, bit 1). In this mode the trickle
charger current is set to approximately 1 mA,
allowing a large backup capacitor to charge more
quickly.
•
In the case where no battery is used, the V
BAK
pin should be tied to V
SS
.
!
Note: systems using lithium batteries should clear
the VBC bit to 0 to prevent battery charging. The
V
BAK
circuitry includes an internal 1 K
Ω
series
resistor as a safety element.
/OSCEN
32.768 kHz
crystal
512 Hz or
SW out
W
Oscillator
Clock
Divider
1 Hz
Update
Logic
CF
Years
8 bits
Months
5 bits
Date
6 bits
Days
3 bits
Hours
6 bits
Minutes
7 bits
Seconds
7 bits
User Interface Registers
R
Figure 2. Real-Time Clock Core Block Diagram
Calibration
When the CAL bit in register 00h is set to ‘1’, the
clock enters calibration mode. In calibration mode,
the ACS output pin is dedicated to the calibration
function and the power fail output is temporarily
unavailable. Calibration operates by applying a
digital correction to the counter based on the
frequency error. In this mode, the ACS pin is driven
with a 512 Hz (nominal) square wave. Any measured
deviation from 512 Hz translates into a timekeeping
error. The user converts the measured error in ppm
and writes the appropriate correction value to the
calibration register. The correction factors are listed
in the table below. Positive ppm errors require a
negative adjustment that removes pulses. Negative
ppm errors require a positive correction that adds
pulses. Positive ppm adjustments have the CALS
(sign) bit set to ‘1’, whereas negative ppm
adjustments have CALS = 0. After calibration, the
clock will have a maximum error of
±
2.17 ppm or
±
0.09 minutes per month at the calibrated
temperature.
The calibration setting is battery-backed and must be
reloaded should the backup source fail. It is accessed
with bits CAL.4-0 in register 01h. This value only
can be written when the CAL bit is set to a ‘1’. To
exit the calibration mode, the user must clear the
CAL bit to a ‘0’. When the CAL bit is ‘0’, the ACS
pin will revert to another function as defined in
Table 3. Control Bit Settings for ACS Pin.
Crystal Type
The crystal oscillator is designed to use a 12.5pF
crystal without the need for external components,
such as loading capacitors. The FM3130 device has
built-in loading capacitors that match the crystal.
If a 32.768kHz crystal is not used, an external
oscillator may be connected to the FM3130. Apply
the oscillator to the X1 pin. Its high and low voltage
levels can be driven rail-to-rail or amplitudes as low
as approximately 500mV p-p. To ensure proper
operation, a DC bias must be applied to the X2 pin.
It should be centered between the high and low levels
on the X1 pin. This can be accomplished with a
voltage divider. See Figure 3.
Rev. 1.0
Sept. 2006
Page 4 of 22
FM3130 Integrated RTC/Alarm with 64Kb FRAM
Vdd
FM3130
R1
X1
R2
choose to drive X1 with an external clock and X2
with an inverted clock using a CMOS inverter.
Layout Recommendations
The X1 and X2 crystal pins employ very high
impedance circuits and the oscillator connected to
these pins can be upset by noise or extra loading. To
reduce RTC clock errors from signal switching noise,
a guard ring should be placed around these pads and
the guard ring grounded. SDA and SCL traces should
be routed away from the X1/X2 pads. The X1 and X2
trace lengths should be less than 5 mm. The use of a
ground plane on the backside or inner board layer is
preferred. See layout example. Red is the top layer,
green is the bottom layer.
Figure 3. External Oscillator
In the example, R1 and R2 are chosen such that the
X2 voltage is centered around the oscillator drive
levels. If you wish to avoid the DC current, you may
X1
X2
VBAK
VSS
X1
X2
VBAK
VSS
Layout for Surface Mount Crystal
(red = top layer, green = bottom layer)
Layout for Through Hole Crystal
(red = top layer, green = bottom layer)
Table 2. Calibration Adjustments
Positive Calibration for slow clocks: Calibration will achieve
±
2.17 PPM after calibration
Measured Frequency Range
Error Range (PPM)
Min
Max
Min
Max
Program Calibration Register to:
512.0000
511.9989
0
2.17
000000
511.9989
511.9967
2.18
6.51
100001
511.9967
511.9944
6.52
10.85
100010
511.9944
511.9922
10.86
15.19
100011
511.9922
511.9900
15.20
19.53
100100
511.9900
511.9878
19.54
23.87
100101
511.9878
511.9856
23.88
28.21
100110
511.9856
511.9833
28.22
32.55
100111
511.9833
511.9811
32.56
36.89
101000
511.9811
511.9789
36.90
41.23
101001
511.9789
511.9767
41.24
45.57
101010
511.9767
511.9744
45.58
49.91
101011
511.9744
511.9722
49.92
54.25
101100
511.9722
511.9700
54.26
58.59
101101
511.9700
511.9678
58.60
62.93
101110
511.9678
511.9656
62.94
67.27
101111
511.9656
511.9633
67.28
71.61
110000
511.9633
511.9611
71.62
75.95
110001
511.9611
511.9589
75.96
80.29
110010
511.9589
511.9567
80.30
84.63
110011
511.9567
511.9544
84.64
88.97
110100
511.9544
511.9522
88.98
93.31
110101
511.9522
511.9500
93.32
97.65
110110
511.9500
511.9478
97.66
101.99
110111
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Rev. 1.0
Sept. 2006
Page 5 of 22
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