www.fairchildsemi.com
FMS3110/3115
Triple Video D/A Converters
3 x 10 bit, 150 Ms/s
Features
•
•
•
•
•
•
•
•
•
•
10-bit resolution
150 megapixels per second
± 0.1% linearity error
Sync and blank controls
1.0V p-p video into 37.5
Ω
or 75
Ω
load
Internal bandgap voltage reference
Double-buffered data for low distortion
TTL-compatible inputs
Low glitch energy
Single +5 Volt power supply
Description
FMS3110/3115 products are low-cost triple D/A converters
that are tailored to fit graphics and video applications where
speed is critical. Two speed grades are available:
FMS3110
FMS3115
100 Ms/s
150 Ms/s
Applications
• Video signal conversion
– RGB
– YC
B
C
R
– Composite, Y, C
• Multimedia systems
• Image processing
• True-color graphics systems (1 billion colors)
• Broadcast television equipment
• High-Definition Television (HDTV) equipment
• Direct digital synthesis
TTL-level inputs are converted to analog current outputs that
can drive 25–37.5
Ω
loads corresponding to doubly-terminated
50–75
Ω
loads. A sync current following SYNC input timing
is added to the I
OG
output. BLANK will override RGB
inputs, setting I
OG
, I
OB
and I
OR
currents to zero when
BLANK = L. Although appropriate for many applications
the internal 1.235V reference voltage can be overridden by
the V
REF
input.
Few external components are required, just the current
reference resistor, current output load resistors, and
decoupling capacitors.
Package is a 48-lead LQFP. Fabrication technology is
CMOS. Performance is guaranteed from 0 to 70°C.
Block Diagram
SYNC
BLANK
SYNC
G
9-0
10
10 bit D/A
Converter
IO
G
B
9-0
10
10 bit D/A
Converter
IO
B
R
9-0
CLOCK
10
10 bit D/A
Converter
IO
R
COMP
R
REF
V
REF
+1.235V
Ref
Rev. 1.07 12/8/04
FMS3110/3115
DATA SHEET
Functional Description
Within the FMS3110/3115 are three identical 10-bit D/A
converters, each with a current source output. External loads
are required to convert the current to voltage outputs. Data
inputs RGB
7-0
are overridden by the BLANK input. SYNC
= H activates, sync current from I
OS
for sync-on-green video
signals.
D/A Outputs
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor connected
between R
REF
and GND.
Normally, a source termination resistor of 75 Ohms is
connected between the D/A current output pin and GND
near the D/A converter. A 75 Ohm line may then be
connected with another 75 Ohm termination resistor at the
far end of the cable. This “double termination” presents the
D/A converter with a net resistive load of 37.5 Ohms.
The FMS3110/3115 may also be operated with a single 75
Ohm terminating resistor. To lower the output voltage swing
to the desired range, the nominal value of the resistor on
R
REF
should be doubled.
Digital Inputs
All digital inputs are TTL-compatible. Data is registered on
the rising edge of the CLK signal. Following one stage of
pipeline delay, the analog output changes t
DO
after the rising
edge of CLK.
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 1
and Table 1) of the D/A converters during CRT retrace
intervals. BLANK forces the D/A outputs to the blanking
level while SYNC = L turns off a current source that is
connected to the green D/A converter. SYNC = H adds a 40
IRE sync pulse to the green output, SYNC = L sets the green
output to 0.0 Volts during the sync tip. SYNC and BLANK
are registered on the rising edge of CLK.
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference voltage
is +1.235 Volts with a 3K
Ω
source resistance. An external
voltage reference may be connected to the V
REF
pin,
overriding the internal voltage reference.
A 0.1µF capacitor must be connected between the COMP
pin and V
DD
to stabilize internal bias circuitry and ensure
low-noise operation.
Power and Ground
data: 660 mV max.
pedestal: 54 mV
sync: 286 mV
Required power is a single +5.0 Volt supply. To minimize
power supply induced noise, analog +5V should be connected
to V
DD
pins with 0.1 and 0.01 µF decoupling capacitors
placed adjacent to each V
DD
pin or pin pair.
The high slew-rate of digital data makes capacitive coupling
to the outputs of any D/A converter a potential problem.
Since the digital signals contain high-frequency components
of the CLK signal, as well as the video output signal, the
resulting data feedthrough often looks like harmonic
distortion or reduced signal-to-noise performance. All
ground pins should be connected to a common solid ground
plane for best performance.
Figure 1. Nominal Output Levels
2
REV. 1.07 12/8/04
DATA SHEET
FMS3110/3115
Table 1. Output Voltage Versus Input Code, SYNC and BLANK
V
REF
= 1.235 V, R
REF
= 590
Ω
, R
L
= 37.5
Ω
Blue and Red D/As
RGB
9-0
(MSB…LSB)
11 1111 1111
11 1111 1111
11 1111 1110
11 1111 1101
•
•
10 0000 0000
01 1111 1111
•
•
00 0000 0010
00 0000 0001
00 0000 0000
XX XXXX XXXX
XX XXXX XXXX
SYNC
X
X
X
X
•
•
X
X
•
•
X
X
X
X
X
BLANK
1
1
1
1
•
•
1
1
•
•
1
1
1
0
0
V
OUT
0.7140
0.7140
0.7134
0.7127
•
•
0.3843
0.3837
•
•
0.0553
0.0546
0.0540
0.0000
0.0000
SYNC
1
0
1
1
•
•
1
1
•
•
1
1
1
1
0
Green D/A
BLANK
1
1
1
1
•
•
1
1
•
•
1
1
1
0
0
V
OUT
1.0000
0.7140
0.9994
0.9987
•
•
0.6703
0.6697
•
•
0.3413
0.3406
0.3400
0.2860
0.0000
Pin Assignments
G
0
G
0
R9
R9
R8
R8
R7
R7
R6
R6
R5
R5
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
NC
NC
48
48
47
47
46
46
45
45
44
44
43
43
42
42
41
41
40
40
39
39
38
38
37
37
36
35
34
33
32
31
30
29
28
27
26
25
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLANK
SYNC
VDD
1
2
3
4
5
6
7
8
9
10
11
12
LQFP
FMS3110/3115
RREF
VREF
COMP
IOR
IOG
OVDD
VDD
VDD
IOB
GND
GND
CLOCK
NC
NC
NC
B0
B0
B1
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
NC
NC
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
Rev. 1.07 12/8/04
3
FMS3110/3115
DATA SHEET
Pin Descriptions
Pin Name
CLK
Pin Number
26
Value
TTL
Description
Clock Input.
The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended that CLK be
driven by a dedicated TTL buffer to avoid reflection induced jitter,
overshoot, and undershoot.
Red Pixel Data Inputs.
TTL-compatible Red Data Inputs are
registered on the rising edge of CLK.
Green Pixel Data Inputs.
TTL-compatible Green Data Inputs are
registered on the rising edge of CLK.
Blue Pixel Data Inputs.
TTL-compatible Blue Data Inputs are
registered on the rising edge of CLK.
Sync Pulse Input.
Bringing SYNC LOW, turns off a 40 IRE (7.62 mA)
current source which forms a sync pulse on the Green D/A converter
output. SYNC is registered on the rising edge of CLK with the same
pipeline latency as BLANK and pixel data. SYNC does not override
any other data and should be used only during the blanking interval.
Since this is a single-supply D/A and all signals are positive-going,
sync is added to the bottom of the Green D/A range. So turning SYNC
OFF means turning the current source ON. When a sync pulse is
desired, the current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC should be
connected to GND.
BLANK
10
TTL
Blanking Input.
When BLANK is LOW, pixel inputs are ignored and
the D/A converter outputs fall to the blanking level. BLANK is
registered on the rising edge of CLK and has the same pipeline
latency as SYNC.
Red Current Output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
Green Current Output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines. Sync pulses may be
added to the Green D/A output.
Blue Current Output.
The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M compatible
levels into doubly-terminated 75 Ohm lines.
Clock and Pixel I/O
R
9-0
G
9-0
B
9-0
Controls
SYNC
47-37
48, 9–1
23–14
TTL
TTL
TTL
11
TTL
Video Outputs
IO
R
33
0.714 V
p-p
IO
G
32
1 V
p-p
IO
B
29
0.714 V
p-p
4
Rev. 1.07 12/8/04
DATA SHEET
FMS3110/3115
Pin Descriptions
(continued)
Pin Name
V
REF
Pin Number
35
Value
+1.235 V
Description
Voltage Reference Output/Input.
An internal voltage source of
+1.235 Volts is output on this pin. An external +1.235 Volt reference
may be applied here which overrides the internal reference.
Decoupling V
REF
to GND with a 0.1µF ceramic capacitor is required.
Current-Setting Resistor.
Full-scale output current of each D/A
converter is determined by the value of the resistor connected
between R
REF
and GND. Nominal value of R
REF
is found from:
R
REF
= 9.1 (V
REF
/I
FS
)
where I
FS
is the full-scale (white) output current (in amps) from the
D/A converter (without sync). Sync is 0.4 * I
FS
.
D/A full-scale (white) current may also be calculated from:
I
FS
= V
FS
/R
L
Where V
FS
is the white voltage level and R
L
is the total resistive load
(in ohms) on each D/A converter. V
FS
is the blank to full-scale
voltage.
COMP
34
0.1 µF
Compensation Capacitor.
A 0.1 µF ceramic capacitor must be
connected between COMP and V
DD
to stabilize internal bias circuitry.
Power Supply.
Ground.
Voltage Reference
R
REF
36
560
Ω
Power and Ground
V
DD
GND
12, 30, 31
27, 28
+5 V
0.0V
Equivalent Circuits
V
DD
V
DD
p
Digital
Input
n
n
V
DD
p
OUT
GND
GND
Figure 2. Equivalent Digital Input Circuit
Figure 3. Equivalent Analog Output Circuit
Rev. 1.07 12/8/04
5
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