A48P3616A
Preliminary
Features
CAS Latency and Frequency
CAS
Latency
2
2.5
3
4
Maximum Operating Frequency (MHz)
DDR500 (4)
133
200
250
250
DDR400 (5)
133
166
200
-
Differential clock inputs (CK and
CK
)
Four internal banks for concurrent operation.
Data mask (DM) for write data.
DLL aligns DQ and DQ
S
transitions with CK transitions.
Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQ
S
.
Burst lengths: 2, 4, or 8
CAS Latency: 2/2.5/3/4
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
4096 refresh cycles / 64ms (4 banks concurrent refresh)
2.5V (SSTL_2 compatible) I/O
V
DD
= V
DDQ
= 2.5V ± 0.2V
Industrial operating temperature range: -40ºC to +85ºC
for -U series.
Available Lead Free packaging
All Pb-free (Lead-free) products are RoHS compliant
8M X 16 Bit DDR DRAM
Double data rate architecture: two data transfers per
clock cycle.
Bidirectional data strobe (DQ
S
) is transmitted and
received with data, to be used in capturing data at the
receiver.
DQ
S
is edge-aligned with data for reads and is center-
aligned with data for writes.
General Description
The 128Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access for
the 128Mb DDR SDRAM effectively consists of a single 2n-
bit wide, one clock cycle data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
A bidirectional data strobe (DQ
S
) is transmitted externally,
along with data, for use in data capture at the receiver. DQ
S
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQ
S
is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQ
S
, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by
hiding row pre-charge and activation time.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class
II compatible.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
PRELIMINARY (July, 2010, Version 0.0)
1
AMIC Technology, Corp.
A48P3616A
Pin Descriptions
Symbol
Type
Description
Clock:
CK and
CK
are differential clock inputs. All address and control input signals
CK,
CK
Input
are sampled on the crossing of the positive edge of
CK
and negative edge of CK.
Output (read) data is referenced to the crossings of CK and
CK
(both directions of
crossing).
Clock Enable:
CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Precharge Power Down and Self Refresh operation (all banks idle), or Active Power
Down (row Active in any bank). CKE is synchronous for power down entry and exit,
and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be
maintained high throughout read and write accesses. Input buffers, excluding CK,
CKE
Input
CK
and CKE are disabled during Power Down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select:
All commands are masked when CS is registered high. CS provides
CS
Input
for external bank selection on systems with multiple banks. CS is considered part of
the command code.
Command Inputs:
RAS
,
CAS
,
WE (along with
CS
) define the command being
entered.
Input Data Mask:
DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM
is sampled on both edges of DQ
S
. Although DM pins are input only, the DM loading
matches the DQ and DQ
S
loading. During a Read, DM can be driven high, low, or
floated. LDM corresponds to the data on DQ
0
-DQ
7
; UDM corresponds to the data on
DQ
8
-DQ
15
.
Bank Address Inputs:
BA0 and BA1 define to which bank an Active, Read, Write or
Precharge command is being applied. BA0 and BA1 also determines if the mode
register or extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs:
Provide the row address for Active commands, and the column
address and Auto Precharge bit for Read/Write commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 low) or all
banks (A10 high). If only one bank is to be precharged, the bank is selected by BA0,
BA1. The address inputs also provide the op-code during a Mode Register Set
command.
Data Input/Output:
Data bus.
Data Strobe:
Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data. LDQS corresponds to the
data on DQ
0
-DQ
7
; UDQS corresponds to the data on DQ
8
-DQ
15
No Connect:
No internal electrical connection is present.
DQ Power Supply:
2.5V
±
0.2V.
DQ Ground
Power Supply:
2.5V
±
0.2V.
Ground
SSTL_2 reference voltage:
(V
DDQ
/ 2)
±
1%.
RAS
,
CAS
,
WE
Input
UDM, LDM
Input
BA0, BA1
Input
A0-A11
Input
DQ
LDQS, UDQS
NC
V
DDQ
V
SSQ
V
DD
V
SS
V
REF
Input / Output
Input / Output
Supply
Supply
Supply
Supply
Supply
PRELIMINARY (July, 2010, Version 0.0)
4
AMIC Technology, Corp.
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