Low Skew, 1-to-2,
Differential-to-LVCMOS/LVTTL Fanout
Datasheet
83026I
General Description
The 83026I is a low skew, 1-to-2 Differential-to- LVCMOS/LVTTL
Fanout Buffer and a member of the family of High Performance
Clock Solutions from IDT.The differential input can accept most
differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL)
and translate to two single-ended LVCMOS/LVTTL outputs with a
maximum output skew of 20ps. The small 8-lead SOIC footprint
makes this device ideal for use in applications with limited board
space.
Features
•
•
•
•
•
•
•
•
•
•
•
Two LVCMOS/LVTTL outputs
Differential CLK/nCLK input pair
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency: 350MHz (typical)
Output skew: 20ps (maximum)
Part-to-part skew: 600ps (maximum)
Additive phase jitter, RMS: 0.092ps (typical)
Small 8 lead SOIC package saves board space
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK
Pulldown
nCLK
Pullup
Q1
Q0
Pin Assignment
nc
CLK
nCLK
nc
1
2
3
4
8
7
6
5
V
DD
Q0
Q1
GND
83026I
8-Lead SOIC, 150Mil
3.9mm x 4.9mm x 1.375mm package body
M Package
Top View
©2015 Integrated Device Technology, Inc
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December 15, 2015
83026I Datasheet
Table 1. Pin Descriptions
Number
1, 4
2
3
5
6
7
8
Name
nc
CLK
nCLK
GND
Q1
Q0
V
DD
Unused
Input
Input
Power
Output
Output
Power
Pulldown
Pullup
Type
Description
No connect.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Positive supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
V
DD
= 3.6V
5
Test Conditions
Minimum
Typical
4
51
51
23
7
12
Maximum
Units
pF
k
k
pF
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83026I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
112.7C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
35
Units
V
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
V
DD
= 3.6V
V
DD
= 3.6V or 2.625V
Minimum
2.6
0.5
Typical
Maximum
Units
V
V
NOTE 1: Outputs terminated with 50 to V
DD
/2. See Parameter Measurement Information,
Output Load Test Circuit Diagrams.
Table 3C. Differential DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
nCLK
Input High Current
CLK
nCLK
I
IL
V
PP
V
CMR
Input Low Current
CLK
Peak-to-Peak Input Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
IN
= V
DD
= 3.6V
V
IN
= V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
V
IN
= 0V, V
DD
= 3.6V
-150
-5
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
©2015 Integrated Device Technology, Inc
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83026I Datasheet
AC Electrical Characteristics
Table 4. AC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
125MHz, Integration Range
(12kHz – 20MHz)
0.8V to 2V
150
40
0.092
300
50
450
60
ƒ
350MHz
1.7
Test Conditions
Minimum
Typical
350
2.1
5
2.5
20
600
Maximum
Units
MHz
ns
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DD
/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc
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83026I Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 125MHz
12kHz to 20MHz = 0.092ps (typical)
SSB Phase Noise dBc/Hz
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
©2015 Integrated Device Technology, Inc
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December 15, 2015
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