12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer
Datasheet
85352
General Description
The 85352 is a 12 bit, 2-to-1 LVPECL Clock Buffer. Individual input
select controls support independent multiplexer operation from a
common clock input source. Clock inputs accept most standard
differential levels.
The 85352 is characterized at full 3.3V or mixed 3.3V core/2.5V
output operating supply modes.
Features
•
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Twelve, 2-to-1 multiplexers with LVPECL outputs
Selectable differential CLKx, nCLKx input pairs
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Individual select control for each multiplexer
Select inputs accept LVCMOS / LVTTL levels
Propagation delay: 2ns (maximum)
Additive Phase Jitter, RMS: 0.21ps (typical), 3.3V
Full 3.3V or mixed 3.3V core/2.5V output supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
SEL0:SEL11
Pulldown
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
nCLK1
Pullup/Pulldown
12
Pin Assignment
V
CCO
CLK1
nCLK1
SEL8
SEL7
SEL6
SEL0
SEL1
SEL2
CLK0
nCLK0
V
CCO
0
Q0
nQ0
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q11
nQ11
1
0
48 47 46 45 44 43 42 41 40
39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
85352
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
V
CCO
V
EE
V
CC
SEL11
SEL10
SEL9
SEL3
SEL4
SEL5
V
CC
V
EE
V
CCO
1
85352
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision D, December 1, 2015
85352 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9,
10
11, 12
25, 26
27, 28
29, 30
31, 32
33, 34
35, 36
13, 24, 37, 48
14, 23
15, 22
16, 17,
18, 19,
20, 21,
40, 41,
42, 43,
44, 45
38
39
46
47
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
nQ11, Q11
nQ10, Q10
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
V
CCO
V
EE
V
CC
SEL5, SEL4,
SEL3, SEL9,
SEL10, SEL11,
SEL8, SEL7,
SEL6, SEL0,
SEL1, SEL2
CLK1
nCLK1
CLK0
nCLK0
Type
Description
Output
Differential output pairs. LVPECL interface levels.
Power
Power
Power
Output power supply pins.
Negative power supply pins.
Positive power supply pins.
Input
Pulldown
Clock select inputs. LVCMOS / LVTTL interface levels. See Table 3.
Input
Input
Input
Input
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table
3.
Control Input Function Table
SELx
0
1
Selected Clock inputs
CLK0, nCLK0
CLK1, nCLK1
©2015 Integrated Device Technology, Inc.
2
Revision C, December 1, 2015
85352 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
27.6°C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
=
3.3V
± 5%, V
CCO
= 2.5V to
3.3V
±5%, V
EE
= 0V, T
A
= -40°C to
85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
3.3
Maximum
3.465
3.465
170
Units
V
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, V
CC
=
3.3V
± 5%, V
CCO
= 2.5V to
3.3V
±5%, V
EE
= 0V, T
A
= -40°C to
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL[0:11]
SEL[0:11]
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
Table 4C. Differential Input DC Characteristics, V
CC
=
3.3V
± 5%, V
CCO
= 2.5V to
3.3V
±5%, V
EE
= 0V, T
A
= -40°C to
85°C
Symbol
I
IH
Parameter
CLK0, CLK1
Input High Current
nCLK0, nCLK1
CLK0, CLK1
I
IL
V
PP
V
CMR
Input Low Current
nCLK0, nCLK1
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
-150
0.15
V
EE
+ 0.5
1.0
V
CC
– 0.85
µA
V
V
-5
150
µA
µA
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
©2015 Integrated Device Technology, Inc.
3
Revision C, December 1, 2015
85352 Datasheet
Table 4D. LVPECL DC Characteristics, V
CC
=
3.3V
± 5%, V
CCO
= 2.5V to
3.3V
±5%, V
EE
= 0V, T
A
= -40°C to
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
– 1.4
V
CCO
– 2.0
0.6
Typical
Maximum
V
CCO
– 0.9
V
CCO
– 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
AC Electrical Characteristics
Table 5A. AC Electrical Characteristics, V
CC
= V
CCO
=
3.3V
± 5%, V
EE
= 0V, T
A
= -40°C to
85°C
Symbol
f
MAX
Parameter
Output Frequency
Test Conditions
Minimum
1.0
Typical
1.5
0.21
Maximum
700
2.0
Units
MHz
ns
ps
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS:
refer to additive Phase Jitter Section
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2, 4
Output Rise/ Fall Time
Output Duty Cycle
20% to 80%
ƒ
622MHz
156.25MHz
Integration Range: (12kHz – 20MHz)
180
750
150
45
700
55
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 5B. AC Electrical Characteristics, V
CC
=
3.3V
± 5%, V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to
85°C
Symbol
f
MAX
Parameter
Output Frequency
Test Conditions
Minimum
1.0
Typical
1.5
0.23
Maximum
700
2.0
Units
MHz
ns
ps
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 2, 4
Output Rise/ Fall Time
Output Duty Cycle
20% to 80%
ƒ
622MHz
156.25MHz
Integration Range: (12kHz – 20MHz)
180
750
150
45
700
55
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
©2015 Integrated Device Technology, Inc.
4
Revision C, December 1, 2015
85352 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.21ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator “Rohde & Schwarz Signal Generator
SMA100A
9kHz
– 6GHz as external input to a Hewlett Packard
8133A 3GHz Pulse Generator".
©2015 Integrated Device Technology, Inc.
5
Revision C, December 1, 2015
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