DATASHEET
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Description
The ICS671-03 is a low phase noise, high speed PLL
based, 8 output, low skew zero delay buffer. Based on IDT’s
proprietary low jitter Phase Locked Loop (PLL) techniques,
the device provides eight low skew outputs at speeds up to
133 MHz at 3.3 V. The outputs can be generated from the
PLL (for zero delay), or directly from the input (for testing),
and can be set to tri-state mode or to stop at a low level. For
normal operation as a zero delay buffer, any output clock is
tied to the FBIN pin.
ICS671-03
Features
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Packaged in 16 pin narrow (150 mil) SOIC
Clock outputs from 10 to 133 MHz
Zero input-output delay
Eight low-skew (<200 ps) outputs
Device-to-device skew <700 ps
Low jitter (<200 ps)
Full CMOS outputs with 25 mA output drive capability at
TTL levels
5 V tolerant FBIN and CLKIN pins
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
3.3 V operating voltage
Industrial temperature range of -40 to 85 °C
RoHS compliant (Pb free) package
Block Diagram
IDT™
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
1
ICS671-03
REV D 051310
ICS671-03
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ZDB AND MULTIPLIER
Pin Assignment
Output Clock Mode Select Table
S2 S1
0
0
1
1
0
1
0
1
CLKA1:A4
Tri-state (note 1)
Stopped Low
Running
Running
CLKB1:B4
Tri-state (note 1)
Stopped Low
Running
Running
A & B Source
PLL
None
CLKIN (note 2)
PLL
PLL Status
ON
OFF
OFF
ON
Note 1: Outputs are in high impedance state with weak pulldowns.
Note 2: Buffer mode only; not zero delay between input and output.
Pin Descriptions
Pin
Number
1
2, 3, 14, 15
4, 13
5, 12
6, 7, 10, 11
8
9
16
Pin
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
FBIN
Pin
Type
Input
Output
Power
Power
Output
Input
Input
Input
Clock Input (5 V tolerant).
Pin Description
Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.
Power supply. Connect both pins to 3.3 V.
Connect to ground.
Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Feedback Input. Connect to any output under normal operation (5 V tolerant).
Note: Outputs have a weak internal pull-down when in tri-state mode.
IDT™
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
2
ICS671-03
REV D 051310
ICS671-03
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ZDB AND MULTIPLIER
External Components
The ICS671-03 requires a minimum number of external
components for proper operation. Decoupling capacitors of
0.01µF should be connected between VDD and GND on
pins 4 and 5, and VDD and GND on pins 13 and 12, as close
to the device as possible. A series termination resistor of 33
Ω
may be used close to each clock output pin to reduce
reflections.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND, as close to these pins as possible.
For optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS671-03. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
IDT™
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
3
ICS671-03
REV D 051310
ICS671-03
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ZDB AND MULTIPLIER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS671-03. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND)
Inputs and Clock Outputs (referenced to GND)
CLKIN and FBIN Inputs
Storage Temperature
Junction Temperature
Soldering Temperature
Ambient Operating Temperature
Electrostatic Discharge (MIL-STD-883)
-0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V
-0.5 V to 5.5 V
-65 to +150° C
125° C
260° C
-40 to +85
°
C
2000 V min.
IDT™
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
4
ICS671-03
REV D 051310
ICS671-03
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ZDB AND MULTIPLIER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage,
CMOS level
Output Low Voltage
Operating Supply Current
Power Down Supply
Current
Short Circuit Current
Input Capacitance
Symbol
VDD
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
IDD
I
OS
C
IN
Conditions
Min.
3.00
2
Typ.
Max.
3.60
0.8
Units
V
V
V
V
V
I
OH
= -12 mA
I
OH
= -8 mA
I
OL
= 12 mA
No load, S2=1, S1=1,
Note 1
CLKIN=0, S2=0, S1=0
CLKIN=0, Note 2
Each output
S2, S1, FBIN
2.4
VDD-0.4
0.4
70
1.3
1.3
±50
5
V
mA
mA
mA
mA
pF
Note 1: With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz.
Note 2: When there is no clock signal present at CLKIN, the ICS671-03 will enter a power down mode. The PLL is
stopped and the outputs are tri-state.
IDT™
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
5
ICS671-03
REV D 051310
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