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54FCT574CTDB

产品描述Registers Octal D Register
产品类别逻辑    逻辑   
文件大小56KB,共7页
制造商IDT (Integrated Device Technology)
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54FCT574CTDB概述

Registers Octal D Register

54FCT574CTDB规格参数

参数名称属性值
Brand NameIntegrated Device Technology
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码CDIP
包装说明DIP, DIP20,.3
针数20
制造商包装代码CD20
Reach Compliance Codenot_compliant
ECCN代码EAR99
Samacsys DescriptionCERDIP 300 MIL
其他特性BROADSIDE VERSION OF 374
系列FCT
JESD-30 代码R-XDIP-T20
JESD-609代码e0
长度25.3365 mm
负载电容(CL)50 pF
逻辑集成电路类型BUS DRIVER
最大I(ol)0.032 A
湿度敏感等级1
位数8
功能数量1
端口数量2
端子数量20
最高工作温度125 °C
最低工作温度-55 °C
输出特性3-STATE
输出极性TRUE
封装主体材料UNSPECIFIED
封装代码DIP
封装等效代码DIP20,.3
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)240
电源5 V
Prop。Delay @ Nom-Sup6.2 ns
传播延迟(tpd)6.2 ns
认证状态Not Qualified
筛选级别MIL-STD-883 Class B
座面最大高度5.08 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层Tin/Lead (Sn/Pb)
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
触发器类型POSITIVE EDGE
宽度7.62 mm
Base Number Matches1

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IDT54/74FCT574T/AT/CT
FAST CMOS OCTAL D REGISTERS (3-STATE)
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL D
REGISTERS (3-STATE)
IDT54/74FCT574T/AT/CT
FEATURES:
Std., A, and C grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT574T is an 8-bit register built using an advanced dual metal
CMOS technology. These registers consist of eight D-type flip-flops with a
buffered common clock and buffered 3-state output control. When the output
enable (OE) input is low, the eight outputs are enabled. When the
OE
input
is high, the outputs are in the high-impedance state.
Input data meeting the set-up and hold time requirements of the D inputs
is transferred to the Q outputs on the low-to-high transition of the clock input.
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
CP D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
OE
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
NOVEMBER 2016
DSC-5494/7
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

 
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