74ABT646A
Octal bus transceiver/register; 3-state
Rev. 03 — 15 March 2010
Product data sheet
1. General description
The 74ABT646A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT646A transceiver/register consists of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of
data directly from the input bus or the internal registers. Data on the A bus or B bus will be
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.
Output Enable (OE) and Direction (DIR) pins are provided to control the transceiver
function. In the transceiver mode, data present at the high-impedance port may be stored
in either the A or B register or both.
The Select (SAB, SBA) pins determine whether data is stored or transferred through the
device in real-time. The DIR pin determines which bus receives data when OE is active
(LOW). In isolation mode (OE = HIGH), data from bus A may be stored in the B register
and/or data from bus B may be stored in the A register. When an output function is
disabled, the input function is still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time. The examples in
Figure 5
“Real time bus transfer and storage” on page 6
demonstrate the four fundamental bus
management functions that can be performed with the 74ABT646A.
2. Features and benefits
I
I
I
I
I
I
I
I
I
Combines 74ABT245 and 74ABT373A type functions in one device
Independent registers for A and B buses
Multiplexed real-time and stored data
Live insertion and extraction permitted
Output capability: +64 mA to
−32
mA
Power-up 3-state
Power-up reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
N
HBM JESD22-A114F exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
NXP Semiconductors
74ABT646A
Octal bus transceiver/register; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74ABT646AD
74ABT646ADB
74ABT646APW
−40 °C
to +85
°C
−40 °C
to +85
°C
−40 °C
to +85
°C
Name
SO24
SSOP24
TSSOP24
Description
Version
Type number
plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
plastic shrink small outline package; 24 leads;
body width 5.3 mm
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT340-1
SOT355-1
4. Functional diagram
21
G3
3EN1[BA]
3
22
4
5
6
7
8
9
10 11
2
23
1
2
3
23
22
21
A0 A1 A2 A3 A4 A5 A6 A7
CPAB
SAB
DIR
CPBA
SBA
OE
B0 B1 B2 B3 B4 B5 B6 B7
20 19 18 17 16 15 14 13
001aae891
3EN2[AB]
G6
G7
C4
C5
≥1
7
7
6
6
≥1
4D
1
2
19
18
17
16
15
14
13
001aae892
1
4
20
1
5D
5
6
7
8
9
10
11
1
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
2 of 19
NXP Semiconductors
74ABT646A
Octal bus transceiver/register; 3-state
OE
21
DIR
CPBA
SBA
CPAB
SAB
3
23
22
1
2
1 of 8 channels
1D
C1
Q
A0
4
1D
C1
Q
20
B0
A1
A2
A3
A4
A5
A6
A7
5
6
7
8
9
10
11
DETAIL A
×
7
19
18
17
16
15
14
13
001aae894
B1
B2
B3
B4
B5
B6
B7
Fig 3.
Logic diagram
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
3 of 19
NXP Semiconductors
74ABT646A
Octal bus transceiver/register; 3-state
5. Pinning information
5.1 Pinning
74ABT646A
CPAB
SAB
DIR
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OE
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
001aae890
A6 10
A7 11
GND 12
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
CPAB
SAB
DIR
A0, A1, A2, A3, A4, A5, A6, A7
GND
B0, B1, B2, B3, B4, B5, B6, B7
OE
SBA
CPBA
V
CC
Pin description
Pin
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
12
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
24
Description
A to B clock input
A to B select input
direction control input
data input/output (A side)
ground (0 V)
data input/output (B side)
output enable input (active LOW)
B to A select input
B to A clock input
positive supply voltage
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
4 of 19
NXP Semiconductors
74ABT646A
Octal bus transceiver/register; 3-state
6. Functional description
Table 3.
Inputs
OE
X
X
H
H
L
L
L
L
[1]
Function table
[1]
Data I/O
DIR
X
X
X
X
L
L
H
H
CPAB
↑
X
↑
H or L
X
X
X
H or L
CPBA
X
↑
↑
H or L
X
H or L
X
X
SAB
X
X
X
X
X
X
L
H
SBA
X
X
X
X
L
H
X
X
An
input
unspecified
output
[2]
input
input
output
output
input
input
Bn
unspecified
output
[2]
input
input
input
input
input
output
output
store A, B unspecified
store B, A unspecified
store A and B data
isolation, hold storage
real time B data to A bus
stored B data to A bus
real time A data to B bus
stored A data to B bus
Operating mode
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑
= LOW-to-HIGH clock transition;
The data output function may be enabled or disabled by various signals at the OE input. Data input functions are always enabled,
i.e. data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.
[2]
74ABT646A_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 15 March 2010
5 of 19
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