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74LVC1G00FS3-7

产品描述Logic Gates Single 2 Input POS NAND 1.65V to 5.5V
产品类别逻辑    逻辑   
文件大小462KB,共16页
制造商Diodes Incorporated
标准
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74LVC1G00FS3-7概述

Logic Gates Single 2 Input POS NAND 1.65V to 5.5V

74LVC1G00FS3-7规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Diodes Incorporated
Reach Compliance Codecompliant
Factory Lead Time19 weeks
系列LVC/LCX/Z
JESD-30 代码S-PDSO-N4
JESD-609代码e4
长度0.8 mm
逻辑集成电路类型NAND GATE
湿度敏感等级1
功能数量1
输入次数2
端子数量4
最高工作温度125 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码HVSON
封装形状SQUARE
封装形式SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)260
传播延迟(tpd)10.5 ns
座面最大高度0.35 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级AUTOMOTIVE
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式NO LEAD
端子节距0.48 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度0.8 mm

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74LVC1G00
SINGLE 2 INPUT POSITIVE NAND GATE
Description
The 74LVC1G00 is a single 2-input positive NAND gate with a
standard push-pull output. The device is designed for operation with a
power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V
allowing this device to be used in a mixed voltage environment. The
device is fully specified for partial power down applications using I
OFF
.
The I
OFF
circuitry disables the output preventing damaging current
backflow when the device is powered down.
Pin Assignments
( Top View )
A
1
B
2
5
Vcc
( Top View )
A
1
B
2
GND
3
5
Vcc
4
Y
GND
3
SOT25 / SOT353
( Top View )
4
Y
SOT553
(Top View )
NEW PRODUCT
The gate performs the positive Boolean function:
A
B
GND
1
2
3
6
5
4
Vcc
NC
Y
½
A
B
or
Y
½
A
B
A
B
GND
1
2
3
8
5
4
Vcc
NC
Y
Y
X1-DFN1010-6
(Type B)
(Top View )
X2-DFN1410-6
( Bottom View )
GND
3
B
2
A
1
A
B
GND
Vcc
2
5
NC
3
4
Y
X2-DFN1010-6
1
6
4
Y
5
NC
6
Vcc
(Top View)
A
1
3
GND
5
Vcc
X2-DFN1409-6
Chip Scale
Alternative
B
2
4
Y
X2-DFN0808-4
Packages not to scale
Features
Wide Supply Voltage Range from 1.65 to 5.5V
± 24mA Output Drive at 3.3V
CMOS low power consumption
I
OFF
Supports Partial-Power-Down Mode Operation
Inputs accept up to 5.5V
ESD Protection Tested per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD 78, Class I
Range of Package Options
Direct Interface with TTL Levels
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Applications
Voltage Level Shifting
General Purpose Logic
Power Down Signal Isolation
Wide array of products such as:
PCs, Networking, Notebooks, Netbooks, PDAs
Tablet Computers, E-readers
Computer Peripherals, Hard Drives, CD/DVD ROM
TV, DVD, DVR, Set-Top Box
Cell Phones, Personal Navigation / GPS
MP3 Players, Cameras, Video Recorders
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
74LVC1G00
Document number: DS32196 Rev. 10 - 2
1 of 16
www.diodes.com
April 2016
© Diodes Incorporated

74LVC1G00FS3-7相似产品对比

74LVC1G00FS3-7 74LVC1G00FX4-7
描述 Logic Gates Single 2 Input POS NAND 1.65V to 5.5V Logic Gates Single 2 Input POS NAND 1.65V to 5.5V
是否Rohs认证 符合 符合
厂商名称 Diodes Incorporated Diodes Incorporated
Reach Compliance Code compliant compliant
Factory Lead Time 19 weeks 19 weeks
系列 LVC/LCX/Z LVC/LCX/Z
JESD-30 代码 S-PDSO-N4 R-PBGA-B6
JESD-609代码 e4 e4
长度 0.8 mm 1.4 mm
逻辑集成电路类型 NAND GATE NAND GATE
湿度敏感等级 1 1
功能数量 1 1
输入次数 2 2
端子数量 4 6
最高工作温度 125 °C 125 °C
最低工作温度 -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 HVSON VFBGA
封装形状 SQUARE RECTANGULAR
封装形式 SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE GRID ARRAY, VERY THIN PROFILE, FINE PITCH
传播延迟(tpd) 10.5 ns 10.5 ns
座面最大高度 0.35 mm 0.4 mm
最大供电电压 (Vsup) 5.5 V 5.5 V
最小供电电压 (Vsup) 1.65 V 1.65 V
标称供电电压 (Vsup) 1.8 V 1.8 V
表面贴装 YES YES
技术 CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE
端子面层 Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式 NO LEAD BALL
端子节距 0.48 mm 0.5 mm
端子位置 DUAL BOTTOM
宽度 0.8 mm 0.9 mm

 
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