FemtoClock
®
NG Triple Universal
Frequency Translator
TM
IDT8T49N366I
DATA SHEET
General Description
The IDT8T49N366I is a triple PLL with FemtoClock
®
NG technology.
The IDT8T49N366I integrates low phase noise Frequency
Translation / Synthesis and Jitter attenuation. It includes alarm and
monitoring functions suitable for networking and communications
applications. The device has three fully independent PLLs. Each PLL
is able to generate any output frequency in the 0.98MHz - 312.5MHz
range and most output frequencies in the 312.5MHz - 1,300MHz
range (see Table 3 for details). A wide range of input reference
clocks may be used as the source for the output frequency.
Each PLL of IDT8T49N366I has three operating modes to support a
very broad spectrum of applications:
1) Frequency Synthesizer
Features
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Fourth generation FemtoClock
®
NG technology
Three fully independent PLLs
Universal Frequency Translator
TM
/Frequency Synthesizer and
Jitter attenuator
Outputs are programmable as LVPECL or LVDS
•
Programmable output frequency: 0.98MHz up to 1,300MHz
Two differential inputs per PLL support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz (Low-Bandwidth mode)
Input frequency range: 16MHz - 710MHz (High-Bandwidth mode)
REFCLK frequency range: 16MHz - 40MHz
Input clock monitor on each PLL will smoothly switch between
redundant input references
Factory-set register configuration for power-up default state
•
•
Synthesizes output frequencies from an external reference
clock REFCLK.
Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
2) High-Bandwidth Frequency Translator
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Power-up default configuration
Configuration customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 161.1328125MHz, using 40MHz REFCLK
(12kHz - 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
RMS phase jitter at 400MHz, using 40MHz REFCLK
(12kHz - 20MHz): 333fs (typical), Synthesizer Mode (Integer FB)
Full 2.5V ±5% supply mode
-40°C to 85°C ambient operating temperature
10mm x 10mm CABGA package
Lead-free (RoHS 6) packaging
3) Low-Bandwidth Frequency Translator
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Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured.
IDT8T49N366AASGI REVISION A JUNE 28, 2013
1
©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet
FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Complete Block Diagram
LOCKA
Output Divider
N
0
x2
PD/LF
FemtoClock® NG
VCO
1995 - 2600 MHz
Feedback Divider
M_INT
CLK0A
nCLK0A
CLK1A
nCLK1A
CLK_SELA
0
1
Q0A
nQ0A
Q1A
nQ1A
M_FRAC
ADC
LF1A
R
3
PD/CP
LF0A
R
S
C
3
P
1
4
M1
C
P
LOCKB
C
S
x2
PD/LF
FemtoClock® NG
VCO
1995 - 2600 MHz
Feedback Divider
M_INT
CLK0B
nCLK0B
CLK1B
nCLK1B
CLK_SELB
0
1
Output Divider
N
Q0B
nQ0B
Q1B
nQ1B
ADC
LF1B
R
3
PD/CP
LF0B
R
S
0
M_FRAC
C
3
P
1
4
M1
C
P
C
S
LOCKC
x2
PD/LF
FemtoClock® NG
VCO
1995 - 2600 MHz
Feedback Divider
M_INT
CLK0C
nCLK0C
CLK1C
nCLK1C
CLK_SELC
0
1
Output Divider
N
Q0C
nQ0C
Q1C
nQ1C
ADC
LF1C
R
3
PD/CP
LF0C
R
S
0
M_FRAC
C
3
P
1
4
M1
C
P
C
S
PLL_BYPASS
REFCLK
SCLK
SDATA
Control Logic
Global Registers
P
T
O
POR
IDT8T49N366AASGI REVISION A JUNE 28, 2013
2
©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet
FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
E5
B7, C7
B6,
C6
G8, G7
F8,
F7
H3, G3
H4,
G4
C8
H7
G2
D6
Name
REFCLK
CLK0A, CLK1A
nCLK0A,
nCLK1A
CLK0B, CLK1B
nCLK0B,
nCLK1B
CLK0C, CLK1C
nCLK0C,
nCLK1C
Rsvd
Rsvd
Rsvd
CLK_SELA
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pulldown
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Reference clock for device operation.
Non-inverting differential clock inputs.
Inverting differential clock inputs. V
CC
/2 default when left floating (set by
the internal pullup and pulldown resistors).
Non-inverting differential clock inputs.
Inverting differential clock inputs. V
CC
/2 default when left floating (set by
the internal pullup and pulldown resistors).
Non-inverting differential clock inputs.
Inverting differential clock inputs. V
CC
2 default when left floating (set by
the internal pullup and pulldown resistors).
Reserved, connect to V
EE.
Reserved, connect to V
EE.
Reserved, connect to V
EE.
Input clock select. Selects the active differential clock input.
0 = CLK0A, nCLK0A (default)
1 = CLK1A, nCLK1A
Input clock select. Selects the active differential clock input.
0 = CLK0B, nCLK0B (default)
1 = CLK1B, nCLK1B
Input clock select. Selects the active differential clock input.
0 = CLK0C, nCLK0C (default)
1 = CLK1C, nCLK1C
Bypasses the DCXO PLL.
0 = PLL Mode (default)
1 = PLL Bypassed
I
2
C Clock Input. LVCMOS/LVTTL interface levels.
Loop filter connection node pins. LF0A is the output, LF1A is the input.
Loop filter connection node pins. LF0B is the output, LF1B is the input.
Loop filter connection node pins. LF0C is the output, LF1C is the input.
Pullup
I
2
C Data Input/Output. Open drain.
Differential output pair.
Output type is programmable to LVDS or LVPECL interface levels.
Differential output pair.
Output type is programmable to LVDS or LVPECL interface levels.
Differential output pair.
Output type is programmable to LVDS or LVPECL interface levels.
Differential output pair.
Output type is programmable to LVDS or LVPECL interface levels.
Differential output pair.
Output type is programmable to LVDS or LVPECL interface levels.
Differential output pair.
Output type is programmable to LVDS or LVPECL interface levels.
Lock Indicator - indicates that PLLA is in a locked condition.
LVCMOS/LVTTL interface levels.
F6
CLK_SELB
Input
Pulldown
F4
CLK_SELC
Input
Pulldown
E6
PLL_BYPASS
Input
Pulldown
G5
D9, E9,
J6, J5
F1, E1
G6
A9, B9
D8, F9
J9, J8
H6, J4
J1, H1
F2, D1
C5
SCLK
LF0A, LF1A
LF0B, LF1B
LF0C, LF1C
SDATA
Q0A, nQ0A
Q1A, nQ1A
Q0B, nQ0B
Q1B, nQ1B
Q0C, nQ0C
Q1C, nQ1C
LOCKA
Input
Analog I/O
Analog I/O
Analog I/O
I/O
Output
Output
Output
Output
Output
Output
Output
Pullup
IDT8T49N366AASGI REVISION A JUNE 28, 2013
3
©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet
FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Table 1. Pin Descriptions
Number
E8
H5
A7
D5
D7
E7
G9
F5
E3
J3
F3
A8, B8, C9
H8, H9, J7
G1, H2, J2
A2-A6, B1-B5,
C1-C4, D2-D4,
E2, E4
Name
LOCKB
LOCKC
V
CCA_A
V
CCO_A
V
CC_A
V
CCA_B
V
CCO_B
V
CC_B
V
CCA_C
V
CCO_C
V
CC_C
V
EE_A
V
EE_B
V
EE_C
nc
Output
Output
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
Description
Lock Indicator - indicates that PLLB is in a locked condition.
LVCMOS/LVTTL interface levels.
Lock Indicator - indicates that PLLC is in a locked condition.
LVCMOS/LVTTL interface levels.
Analog power supply for PLLA.
Output power supply for PLLA.
Core power supply for PLLA.
Analog power supply for PLLB.
Output power supply for PLLB.
Core power supply for PLLB.
Analog power supply for PLLC.
Output power supply for PLLC.
Core power supply for PLLC.
Negative supply for PLLA.
Negative supply for PLLB.
Negative supply for PLLC.
No connect. These pins may be left unconnected.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Input
Pulldown Resistor
Input
Pullup Resistor
REFCLK,
PLL_BYPASS
SDATA,
SCLK
Test Conditions
Minimum
Typical
3.5
51
51
16.66
16.66
Maximum
Units
pF
k
k
k
k
IDT8T49N366AASGI REVISION A JUNE 28, 2013
4
©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet
FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
Pin Assignment
J
H
G
F
E
D
C
B
A
Q0C
V
EE
_
C
V
CCO
_
C
nQ1B
LF1B
LF0B
V
EE
_
B
nQ0B
Q0B
nQ0C
V
EE
_
C
CLK0C
nCLK0C
LOCKC
Q1B
Rsvd
V
EE
_
B
V
EE
_
B
V
EE
_
C
Rsvd
CLK1C
nCLK1C
SCLK
SDATA
CLK1B
CLK0B
V
CCO
_
B
LF0C
Q1C
V
CC
_
C
CLK_
SELC
V
CC
_
B
CLK_
SELB
PLL_
BYP
CLK_
SELA
nCLK1B
nCLK0B
nQ1A
LF1C
nc
V
CCA
_
C
nc
REFCLK
Bottom View
V
CCA
_
B
LOCKB
LF1A
nQ1C
nc
nc
nc
V
CCO
_
A
V
CC
_
A
Q1A
LF0A
nc
nc
nc
nc
LOCKA
nCLK1A
CLK1A
Rsvd
V
EE
_
A
nc
nc
nc
nc
nc
nCLK0A
CLK0A
V
EE
_
A
nQ0A
nc
nc
nc
nc
nc
V
CCA
_
A
V
EE
_
A
Q0A
1
IDT8T49N366I Pin Map
2
3
4
5
6
7
8
9
80-Ball Lead
10mm x 10mm x1mm package body
CABGA Package
(bottom view)
IDT8T49N366AASGI REVISION A JUNE 28, 2013
5
©2013 Integrated Device Technology, Inc.
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