FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers
FAN3216 / FAN3217
Dual 2-A, High-Speed, Low-Side Gate Drivers
Features
Industry-Standard Pinouts
4.5-V to 18-V Operating Range
3-A Peak Sink/Source at V
DD
= 12 V
2.4-A Sink / 1.6-A Source at V
OUT
= 6 V
Inverting Configuration (FAN3216) and
Non-Inverting Configuration (FAN3217)
Internal Resistors Turn Driver Off If No Inputs
12-ns / 9-ns Typical Rise/Fall Times (1 nF Load)
20-ns Typical Propagation Delay Time Matched
w ithin 1 ns to the Other Channel
TTL Input Thresholds
MillerDrive™ Technology
Double Current Capability by Paralleling Channels
Standard SOIC-8 Package
Rated from –40°C to +125°C Ambient
Automotive Qualified to AEC-Q100 (F085 Versions)
Description
The FA N3216 and FAN3217 dual 2 A gate drivers are
designed to drive N-channel enhancement- mode
MOSFETs in low -side sw itching applications by
providing high peak current pulses dur ing the short
sw itching intervals. They are both available w ith TTL
input thresholds. Internal circuitry provides an under-
voltage lockout function by holding the output LOW until
the supply voltage is w ithin the operating range. In
addition, the drivers feature matched internal
propagation delays betw een A and B channels for
applications requir ing dual gate drives w ith critical
timing, such as synchronous rectifiers. This also
enables connecting tw o drivers in parallel to effectively
double the current capability driving a single MOSFET.
The FA N3216/17 drivers incorporate Miller Drive™
architecture for the final output stage. This bipolar-
MOSFET combination provides high current during the
Miller plateau stage of the MOSFET turn-on / turn-off
process to minimize sw itching loss, w hile providing rail-
to-rail voltage sw ing and reverse current capability.
The FAN3216 offers two inverting drivers and the
FA N3217 offers tw o non-inverting drivers. Both are
offered in a standard 8-pin SOIC package.
Applications
Sw itch-Mode Pow er Supplies
High-Efficiency MOSFET Sw itching
Synchronous Rectifier Circuits
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 Versions)
NC
1
INA
2
GND
3
INB
4
B
A
8
7
6
5
NC
OUTA
VDD
OUTB
NC
1
INA
2
GND
3
INB
4
B
A
8
7
6
5
NC
OUTA
VDD
OUTB
Figure 1.
FAN3216 Pin Configuration
Figure 2.
FAN3217 Pin Configuration
Publication Order Number:
FAN3217/D
© 2013 Semiconductor Components Industries, LLC.
October-2017, Rev. 2
FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers
Ordering Information
Part Number
FAN3216TMX
FAN3216TMX_F085
FAN3217TMX
FAN3217TMX_F085
(1)
(1)
Logic
Dual Inverting Channels
Dual Inverting Channels
Dual Non-Inverting Channels
Dual Non-Inverting Channels
Input
Package
Threshold
TTL
TTL
TTL
TTL
SOIC-8
SOIC-8
SOIC-8
SOIC-8
Packing
Method
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Quantity
per Reel
2,500
2,500
2,500
2,500
Note:
1. Qualified to AEC-Q100
Package Outlines
1
8
2
7
3
6
4
5
Figure 3. SOIC-8 (Top View )
Thermal Characteristics
(2)
Package
8-Pin Small Outline Integrated Circuit (SOIC)
JL(3)
40
JT(4)
31
JA(5)
89
JB(6)
43
JT(7)
3.0
Unit
°C/W
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL (
JL
): Thermal resistance betw een the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
4. Theta_JT (
JT
): Thermal resistance betw een the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
5. Theta_JA (Θ
JA
): Thermal resistance betw een junction and ambient, dependent on the PCB design, heat sinking,
and airflow . The value given is for natural convection w ith no heatsink using a 2S2P board, as specified in
JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
6. Psi_JB (jB): Thermal characterization parameter providing correlation betw een semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 5. For
the SOIC-8 package, the board reference is defined as the pcb copper adjacent to pin 6.
7. Psi_JT (jT): Thermal characterization parameter providing correlation betw een the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 5.
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FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers
Pin Configurations
NC
INA
GND
INB
1
2
3
4
8
NC
OUTA
VDD
OUTB
NC
INA
GND
INB
1
2
3
4
8
NC
OUTA
VDD
OUTB
A
7
6
A
7
6
B
5
B
5
Figure 4. FAN3216
Figure 5. FAN3217
Pin Definitions
Pin
1
2
3
4
5
(FAN3216)
5
(FAN3217)
6
7
(FAN3216)
7
(FAN3217)
8
Name
NC
INA
GND
INB
Input to Channel A.
Pin Description
No Connect.
This pin can be grounded or left floating.
Ground.
Common ground reference for input and output circuits.
Input to Channel B.
Gate Drive Output B
(inverted from the input): Held LOW unless required input is
present and V
DD
is above UVLO threshold.
Gate Drive Output B:
Held LOW unless required input(s) are present and V
DD
is above
UVLO threshold.
Supply Voltage.
Provides pow er to the IC.
Gate Drive Output A
(inverted from the input): Held LOW unless required input is
present and V
DD
is above UVLO threshold.
Gate Drive Output A:
Held LOW unless required input(s) are present and V
DD
is above
UVLO threshold.
No Connect.
This pin can be grounded or left floating.
OUTB
OUTB
VDD
OUTA
OUTA
NC
Output Logic
FAN3216 (x=A or B)
INx
0
1
8
(
)
FAN3217 (x=A or B)
INx
0
8
1
(
)
OUTx
1
0
OUTx
0
1
Note:
8. Default input signal if no external connection is made.
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FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers
Block Diagrams
NC
1
V
DD
100k
8
NC
INA
2
7
OUTA
100k
GND
3
UVLO
6
VDD
V
DD
100k
V
DD_OK
INB
4
100k
5
OUTB
Figure 6. FAN3216 Block Diagram
NC
1
8
NC
INA
2
7
OUTA
100k
100k
GND
3
UVLO
6
VDD
V
DD_OK
INB
4
100k
100k
5
OUTB
Figure 7. FAN3217 Block Diagram
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4
FAN3216 / FAN3217 — Dual 2-A, High-Speed, Low-Side Gate Drivers
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
DD
V
IN
V
OUT
T
L
T
J
T
STG
VDD to PGND
INA and INB to GND
OUTA and OUTB to GND
Parameter
Min.
-0.3
Max.
20.0
Unit
V
V
V
ºC
ºC
ºC
GND - 0.3 V
DD
+ 0.3
GND - 0.3 V
DD
+ 0.3
+260
-55
-65
+150
+150
Lead Soldering Temperature (10 Seconds)
Junction Temperature
Storage Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
DD
V
IN
T
A
Supply Voltage Range
Input Voltage INA and INB
Parameter
Min.
4.5
0
-40
Max.
18.0
V
DD
+125
Unit
V
V
ºC
Operating Ambient Temperature
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