NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
DATASHEET
XPHASE3
TM
POL CONTROL IC
DESCRIPTION
The IR3513 Control IC provides overall control of a scalable number of phases along with an internal gate driver,
current sense/sharing, and PWM. This allows the IR3513 to implement a stand-alone single-phase regulator or
interface with additional Phase ICs to develop a power solution with any number of phases. With this arrangement,
the final solution requires only 1 IC per phase to deploy 1 to X phases. Other approaches require a control IC plus 1
to X driver ICs or scalable “all-in-one” ICs that do not utilize all IC pins or circuitry leading to increased solution cost
and size.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0.8V reference supports 0.8V to 5.1V output voltage with +/-0.5% system set point accuracy
Dynamic margin function provides ± 5 % reference offset
1 (stand-alone) to X phase operation with additional Phase IC
Programmable 250 KHz to 9 Mhz daisy-chain digital phase timing provides a per phase switching
frequency of 250 KHz to 1.5 MHz with no external components
Differential remote sense amplifier with 100kohm input impedance
IC bias linear regulator control with programmable output voltage and UVLO
Programmable converter current limit during soft-start, hiccup with delay during normal operation
Over voltage protection communicated to Phase ICs
System over voltage signal protects against failures such as a shorted high side MOSFET
Detection and protection of open remote sense lines
Open control loop protection
7V/2A gate drivers (4A GATEL sink current)
Integrated boot-strap synchronous PFET
Small thermally enhanced 32L 5 x 5mm MLPQ package
APPLICATION CIRCUIT
VIN (8-16V)
Optional
FUSE
ROVP1
SCR
CVCCL
RVCCLDRV
RVCCLFB1
RVCCLFB2
ROVP2
CVCC
Phase IC
Bias Supply
27
30
29
28
26
PHSOUT
25
CLKOUT
32
VCCLDRV
VVCLFB
VCCL
CIN
1
CBST 2
CVCCP
3
4
5
6
7
RCS
CCS
8
PHSIN
VCC
SW
POWER STAGE VIN
31
GATEH
BOOST
VCCP
GATEL
PGND
LGND
CSIN+
LGND
24
23
22
21
20
19
18
17
CSS/DEL
RVREF
ROCSET
CVREF
ROSC
VOUT+
COUT
ROSC/OVP
VOUT-
IR3513
CONTROL
IC
MARGIN
VOSNS+
SS/DEL
VREF
OCSET
IIN
EAOUT
6 Wire
Control Bus
to Phase
ICs
ENABLE
VOSNS-
OVSNS
CSIN-
FB
VOUT
VCCL
PG
9
10
11
12
13
14
15
MARGIN
VOUT REMOTE SENSE -
VOUT REMOTE SENSE +
ROV1
ENABLE
PG
16
RFB2
CFB
RCP
CCP
RFB1
RFB3
CCP1
ROV2
Figure 1 - IR3513 Application Circuit
Page 1
May 11, 2008
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
ORDERING INFORMATION
Device
IR3513MTRPBF
•
* IR3513MPBF
Samples only
Package
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ(5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
PIN DESCRIPTION
PIN#
1
2
3
4
5
6, 24
7
8
9
10
11
PIN SYMBOL
GATEH
BOOST
VCCP
GATEL
PGND
LGND
CSIN+
CSIN-
ENABLE
PG
MARGIN
PIN DESCRIPTION
High-side driver output and input to GATEL non-overlap comparator.
Supply for high-side driver. An internal bootstrap synchronous PFET is connected
between this pin and the VCCP pin.
Supply for low-side driver. An internal bootstrap synchronous PFET is connected
from this pin to the BOOST pin.
Low-side driver output and input to GATEH non-overlap comparator.
Return for low side driver and reference for GATEH non-overlap comparator.
Local Ground for internal circuitry and the IC substrate connection.
Non-Inverting input to the current sense amplifier and input to debug comparator.
Inverting input to the current sense amplifier and input to synchronous rectification
disable comparator.
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float
this pin as the logic state will be undefined.
Open drain output that drives low during startup and under any external fault
condition. Connect external pull-up.
Tri-state input with internal pull-up to 1.425 V. Low/High voltage shifts the Error
Amplifier reference voltage Up/Down 5%. V(MARGIN) should not be biased to a
voltage greater than V(VCCL).
Inverting remote sense amplifier input. Connect to ground at the load.
Non-inverting remote sense amplifier input. Connect to output at the load.
Output of the voltage regulator, power input for clock oscillator circuitry and other
internal circuitry. Connect a decoupling capacitor to LGND.
Remote sense amplifier output.
Over voltage sense input during normal operation.
Inverting input to the Error Amplifier.
Output of the Error Amplifier.
Average current input signal from active and inactive phase IC(s). This pin is also
used to communicate an over voltage condition to the phase IC(s).
An external resistor tied to VREF along with a fixed internal current source
programs the constant output current limit and hiccup over-current thresholds.
Over-current protection can be disabled by programming the threshold higher than
the possible signal on the IIN pin, but no greater than 5V (do not float this pin).
Reference voltage for the Error Amplifier. An external RC network to LGND
programs the margin slew rate and compensates the internal buffer amp.
An external capacitor to LGND programs converter startup and over current
protection delay timing. It is also used to compensate the constant output current
loop during soft start.
12
13
14, 28
15
16
17
18
19
20
VOSEN-
VOSEN+
VCCL
VOUT
OVSNS
FB
EAOUT
IIN
OCSET
21
22
VREF
SS/DEL
Page 2
May 11, 2008
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
PIN DESCRIPTION CONTINUED
23
ROSC/OVP
A resistor to LGND to program the oscillator frequency and the OCSET bias current.
Oscillator frequency equals the phase switching frequency. The pin voltage is 0.6V
during normal operation and higher than 1.6V if over-voltage condition is detected.
Frequency is equivalent to the phase switching frequency multiplied by the number
of phases. Connect to CLKIN pins of phase ICs.
Phase timing output switching at the phase frequency. Connect to PHSIN pin of the
first phase IC.
Feedback input of the phase timing clock. Connect to the PHSOUT pin of the last
phase IC.
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by a resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control an external transistor. The pin
senses the input of the power supply through a resistor at power-up.
Power Input for under voltage lockout (UVLO) detection and supply for internal IC
circuits.
Return for high-side driver and reference for GATEL non-overlap comparator.
25
26
27
29
30
31
32
CLKOUT
PHSOUT
PHSIN
VCCLFB
VCCLDRV
VCC
SW
Page 3
May 11, 2008
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
Operating Junction Temperature……………..0 to 150
o
C
Storage Temperature Range………………….-65
o
C to 150
o
C
MSL Rating………………………………………2
Reflow Temperature…………………………….260
o
C
PIN #
1
2
3
4
5
6, 24
7
8
9
10
11
12
13
14, 28
15
16
17
18
19
20
21
22
23
25
26
27
29
30
31
32
PIN NAME
GATEH
BOOST
VCCP
GATEL
PGND
LGND
CSIN+
CSIN-
ENABLE
PG
MARGIN
VOSEN-
VOSEN+
VCCL
VOUT
OVSNS
FB
EAOUT
IIN
OCSET
VDAC
SS/DEL
ROSC/OVP
CLKOUT
PHSOUT
PHSIN
VCCLFB
VCCLDRV
VCC
SW
V
MAX
34V
34V
8V
8V
0.3V
n/a
8V
8V
3.5V
VCCL + 0.3V
8V
1.0V
8V
8V
8V
8V
8V
8V
8V
8V
3.5V
8V
8V
8V
8V
8V
3.5V
10V
18V
34V
V
MIN
-0.3VDC, -5V
for 100ns
-0.3V
-0.3V
-0.3VDC, -5V
for 100ns
-0.3V
n/a
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V DC, -5V
for 100ns
I
SOURCE
3A for 100ns, 100mA DC
1A for 100ns, 100mA DC
n/a
5A for 100ns, 200mA DC
5A for 100ns, 200mA DC
20mA
1mA
1mA
1mA
1mA
1mA
5mA
5mA
1mA
5mA
1mA
1mA
25mA
5mA
1mA
1mA
1mA
5mA
100mA
10mA
1mA
1mA
1mA
1mA
3A for 100ns, 100mA DC
I
SINK
3A for 100ns, 100mA DC
3A for 100ns, 100mA DC
5A for 100ns, 200mA DC
5A for 100ns, 200mA DC
n/a
1mA
1mA
5mA
1mA
20mA
1mA
1mA
1mA
25mA
25mA
1mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
100mA
10mA
1mA
1mA
50mA
1mA
n/a
Note: Maximum GATEH – SW = 8V, Maximum BOOST – GATEH = 8V
Page 4
May 11, 2008
NOT RECOMMENDED FOR NEW DESIGNS
REPLACEMENT PRODUCT – IR3513ZMTRPBF
IR3513
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V
≤
VCCL
≤
7.5V, 4.75V
≤
VCCP
≤
7.5V, 8V
≤
VCC
≤
16V, -0.3V
≤
VOSEN-
≤
0.3V, 0
o
C
≤
T
J
≤
125
o
C,
7.75 kΩ
≤
R
OSC
≤
50 kΩ
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C. 7.75KΩ
≤
R
OSC
≤
50.0 KΩ, C
SS/DEL
= 0.1µF
+/-10%, C
GATEH
= 3.3nF, C
GATEL
= 6.8nF (unless otherwise specified).
PARAMETER
VREF Reference
System Set-Point Accuracy
(per test circuit in Fig. 2)
Source & Sink Currents
Margin Input Thresholds
MARGIN Float Voltage
MARGIN Pull-up resistor
Oscillator
ROSC Voltage
CLKOUT High Voltage
CLKOUT Low Voltage
CLKOUT Phase Delay
PHSOUT Frequency
PHSOUT Frequency
PHSOUT Frequency
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
Enable Input
Threshold Voltage
Threshold Voltage
Hysteresis
Bias Current
Blanking Time
TEST CONDITION
MARGIN = OPEN
MARGIN = 0V
MARGIN = VCCL
Include OCSET current
Margin Low
Margin High
MIN
796
755
835
50
0.475
2.1
1.325
3
0.575
I(CLKOUT)=-10mA, measure V(VCCL)–
V(CLKOUT)
I(CLKOUT)= 10mA
Measure time from CLKIN < 1V to GATEH
> 1V
R
OSC
=50.0 KΩ
R
OSC
=24.5 KΩ
R
OSC
=7.75 KΩ
I(PHSOUT)= -1mA
I(PHSOUT)= 1mA
Compare to V(VCCL)
ENABLE rising
ENABLE falling
0V
≤
V(ENABLE)
≤
3.3V
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
TYP
800
760
840
88
0.575
2.2
1.425
4
0.600
MAX
804
765
845
116
0.675
2.3
1.55
6
0.625
1
1
125
275
550
1.65
1
1
70
885
835
75
5
400
UNIT
mV
mV
mV
µA
V
V
V
KΩ
V
V
V
ns
kHz
kHz
MHz
V
V
%
mV
mV
mV
µA
ns
40
225
450
1.35
75
250
500
1.50
30
815
765
25
-5
75
50
850
800
50
0
250
Page 5
May 11, 2008
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