Low Skew, 1-to-9
LVCMOS / LVTTL Clock Multiplier
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES NOVEMBER 2, 2016
87950I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The 87950I is a low voltage, low skew 1-9 LVCMOS/LVTTL
Clock Generator. With output frequencies up to 250MHz the
87950I is targeted for high performance clock applications.
Along with a fully integrated PLL the 87950I contains frequency
configurable outputs.
F
EATURES
•
Fully integrated PLL
•
9 single ended 3.3V LVCMOS/LVTTL outputs
•
Selectable CLK or single ended crystal inputs
•
Maximum output frequency: 250MHz
•
Maximum VCO range: 240MHz to 500MHz
•
Cycle-to-cycle jitter: ±100 (typical)
P
IN
A
SSIGNMENT
CLK_SEL
V
DDA
FBDIV_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
XTAL_IN
1
2
3
4
5
6
7
8
XTAL_OUT
32 31 30 29 28 27 26 25
24
23
QC0
V
DDO
QC1
GND
QD0
V
DDO
QD1
GND
PLL_SEL
MR/nOE
V
DDO
GND
GND
QD4
CLK
V
DDO
QB
QA
GND
•
Output skew: 375ps (maximum) all outputs @ same frequen-
cy
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
•
For functional replacement part use 87973i
87950I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
9 10 11 12 13 14 15 16
QD3
V
DDO
QD2
22
21
20
19
18
17
B
LOCK
D
IAGRAM
DIV_SELA Pulldown
Pulldown
PLL_SEL
CLK Pulldown
Pulldown
CLK_SEL
1
0
XTAL_IN
XTAL_OUT
÷2
PHASE
DETECTOR
VCO
240-500MHz
0
÷4
1
÷8
0
QA
OSC
1
0
LPF
÷8/÷16
FBDIV_SEL Pulldown
DIV_SELB Pulldown
QB
1
0
1
QC0
QC1
DIV_SELC Pulldown
MR/nOE Pulldown
QD0
Power-On Reset
0
1
QD1
QD2
QD3
DIV_SELD Pulldown
QD4
REVISION C 11/6/15
1
©2015 Integrated Device Technology, Inc.
87950I DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7, 13, 17,
21, 25, 29
8,
9
10
Name
V
DDA
FBDIV_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
XTAL_IN, XTAL_
OUT
MR/nOE
Power
Input
Input
Input
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Analog supply pin.
Selects divide value for Bank feedback output as described in
Table 3E. LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank D outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Active High Master Reset. Active Low Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are tri-stated (HiZ). When
Pulldown
logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
Output supply pins.
Bank D clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank B clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank A clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL phase detector reference clock input.
Selects between the PLL and the reference clock as the input to the
Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK. When LOW,
Pulldown
selects XTAL_IN, XTAL _OUT. LVCMOS / LVTTL interface levels.
Input
11, 15, 19,
V
DDO
23, 27
12, 14,
QD4, QD3,
16, 18, 20 QD2, QD1, QD0
22, 24
26
28
30
31
32
Pulldown
Power
Output
Output
Output
Output
Input
Input
Input
QC1, QC0
QB
QA
CLK
PLL_SEL
CLK_SEL
NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance (per output)
Input Pulldown Resistor
Output Impedance
5
V
DDA
, V
DDO
= 3.47V
Test Conditions
Minimum
Typical
4
25
51
7
12
Maximum
Units
pF
pF
kΩ
Ω
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
2
REVISION C 11/6/15
87950I DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DDA
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
42.1°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DDA
V
DDO
I
DDA
I
DDO
Parameter
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
15
115
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DDA
=V
IN
= 3.465V
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
±120
Units
V
V
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
DDO
/2.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
15
Test Conditions
Minimum
Typical Maximum
40
50
7
1
Units
MHz
Fundamental
Ω
pF
mW
T
ABLE
6. PLL I
NPUT
R
EFERENCE
C
HARACTERISTICS
,
V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
REF
Parameter
Input Reference Frequency; NOTE 1
Test Conditions
Minimum
15
Typical
Maximum
62.5
Units
MHz
NOTE 1: Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the
CLK input.
REVISION C 11/6/15
5
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
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