RFM products are now
Murata products.
TR7002
•
•
•
•
•
Designed for Short-Range Wireless Data Communications
Supports RF Data Transmission Rates Up to 115.2 kbps
3 V, Low Current Operation plus Sleep Mode
Up to 10 mW Transmitter Power
Complies with Directive 2002/95/EC
418.00 MHz
Hybrid Transceiver
The TR7002 hybrid transceiver is ideal for short-range wireless data applications where robust operation,
small size, low power consumption and low cost are required. The TR7002 employs
Murata's
amplifier-
sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions
are contained in the hybrid, simplifying and speeding design-in. The receiver section of the TR7002 is
sensitive and stable. A wide dynamic range log detector, in combination with digital AGC and a compound
data slicer, provide robust performance in the presence of on-channel interference or noise. Two stages of
SAW filtering provide excellent receiver out-of-band rejection. The transmitter includes provisions for both
on-off keyed (OOK) and amplitude-shift keyed (ASK) modulation. The transmitter employs SAW filtering to
suppress output harmonics, facilitating compliance with FCC/ETSI I-ETS 300 220 and similar regulations.
Absolute Maximum Ratings
Rating
Power Supply and All Input/Output Pins
Non-Operating Case Temperature
Soldering Temperature (10 seconds, 5 cycles maximum)
SM3-20H
Value
-0.3 to +4.0
-50 to +100
260
Units
V
°C
°C
Electrical Characteristics
Characteristic
Operating Frequency
Data Modulation Type
OOK Data Rate
ASK Data Rate
Receiver Performance
Sensitivity, 4.8 kbps, 10-3 BER, AM Test Method
Sensitivity, 4.8 kbps, 10-3 BER, Pulse Test Method
Current, 4.8 kbps
Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method
Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method
Current, 19.2 kbps
Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method
Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method
Current, 115.2 kbps
Receiver Out-of-Band Rejection, ±5% fo
Receiver Ultimate Rejection
Sym
f
o
Notes
Minimum
417.80
Typical
OOK/ASK
Maximum
418.20
Units
MHz
30
576
kb/s
kb/s
1
1
-111
-105
4.2
dBm
dBm
mA
dBm
dBm
mA
dBm
dBm
mA
dB
dB
1
1
-107
-101
4.25
1
1
-102
-96
4.3
R
±5%
R
ULT
2
2
80
100
©2010-2015 by Murata Electronics N.A., Inc.
TR7002 (R) 4/23/15
Page 1 of 15
www.murata.com
Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C)
Characteristic
Sym
Notes
Minimum
Transmitter Performance
Peak RF Output Power, 235 µA TXMOD Current
Peak Current, 235 µA TXMOD Current
2nd - 4th Harmonic Outputs
5th - 10th Harmonic Outputs
Non-harmonic Spurious Outputs
OOK Turn On/Turn Off Times
ASK Output Rise/Fall Times
Logic 0 Input Voltage
Logic 1 Input Voltage
Logic 0 Output Voltage, 1 mA Sink
Logic 1 Output Voltage, 1 mA Source
Sleep Mode Current
Power Supply Voltage Range
Power Supply Voltage Ripple
Ambient Operating Temperature
T
A
-40
I
S
V
CC
2.2
t
ON
/t
OFF
t
TR
/t
TF
P
OL
I
TPL
2
2
2
2
2
3
3
0
0.85 Vcc
0
0.9 Vcc
Typical
10
32
Maximum
Units
dBm
mA
-40
-45
-40
12/6
1.1/1.1
0.15 Vcc
Vcc
0.1 Vcc
Vcc
200
3.7
10
85
dBm
dBm
dBm
µs
µs
V
V
V
V
nA
Vdc
mV
P-P
°C
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
1.
2.
Typical sensitivity data is based on a 10
-3
bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK
receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. The application/test circuit and
component values are shown on the next page.
Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page.
©2010-2015 by Murata Electronics N.A., Inc.
TR7002 (R) 4/23/15
Page 2 of 15
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3G ASH Transceiver Application Circuit
2G Default OOK/ASK Configuration
+3
VDC
RX Data
TX Data
3G ASH Transceiver Application Circuit
3G OOK/ASK Configuration
+3
VDC
RX Data
TX Data
RX Clock
Host
Microcontroller
Host
Microcontroller
R
TH1
R
TH2
L
AT
11
20
C
DCB
C
DCB
R
TH1
R
TH2
19
18
CFG
CLK
17
CFG
DAT
16
VCC
2
15
GND
3
14
RXD
CLK
13
THLD
1
12
THLD
2
RREF
19
CFG
RFIO
18
CFG
CLK
17
CFG
DAT
16
VCC
2
15
GND
3
14
RXD
CLK
13
THLD
1
12
THLD
2
RREF
L
AT
20
CFG
RFIO
TOP VIEW
GND1
VCC
1
2
VCC
3
3
PK
DET
4
BB
OUT
5
CMP
IN
6
RX
DATA
7
TX
MOD
8
TOP VIEW
GND1
VCC
1
2
VCC
3
3
PK
DET
4
BB
OUT
5
CMP
IN
6
RX
DATA
7
TX
MOD
8
11
L
ESD
1
GND2
10
LPF
ADJ
9
L
ESD
1
GND2
10
LPF
ADJ
9
L
RFB
C
BBO
C
RFB
+3
VDC
C
PKD
R
TXM
R
LPF
R
REF
L
RFB
C
BBO
C
RFB
+3
VDC
C
PKD
R
TXM
R
LPF
R
REF
Tranceiver Set-Up, 3.0 Vdc, -40 to +85 °C
Item
Encoded Data Rate
Minimum Signal Pulse
Maximum Signal Pulse
PKDET Capacitor
BBOUT Capacitor
TXMOD Resistor
LPFADJ Resistor
RREF Resistor
THLD2 Resistor
THLD1 Resistor
1
DC Bypass Capacitor
RF Bypass Capacitor
Series Tuning Inductor
Shunt Tuning/ESD Inductor
RF Bypass Bead
Symbol
DR
NOM
SP
MIN
SP
MAX
C
PKD
C
BBO
R
TXM
R
LPF
R
REF
R
TH2
R
TH1
C
DCB
C
RFB
L
AT
L
ESD
L
RFB
OOK
4.8
208.32
833.28
0.022
0.01
9.1
470
100
-
20
4.7
100
56
220
Fair-Rite
OOK
19.2
52.08
208.32
0.0056
0.0027
9.1
160
100
-
20
4.7
100
56
220
Fair-Rite
ASK
115.2
8.68
34.72
820 pF
390 pF
9.1
24
100
100
20
4.7
100
56
220
Fair-Rite
Units
kb/s
µs
µs
µF
µF
K
K
K
K
K
µF
pF
nH
nH
Notes
see pages 1 & 2
single bit
4 bits of same value
±10% ceramic
±10% ceramic
±5%, for 10 dBm output
±5%
±1%
±1%, typical values
±1%, typical values
tantalum
±5% NPO
50 ohm antenna
50 ohm antenna
2506033017YO or equivalent
1.
When using internal data and clock recovery, a THLD1 value of 47K is recommended to minimize start vector “nuisance tripping” due to random noise.
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.
NOTES:
©2010-2015 by Murata Electronics N.A., Inc.
TR7002 (R) 4/23/15
Page 3 of 15
www.murata.com
ASH Transceiver Theory of Operation
Introduction
Murata's
amplifier-sequenced hybrid (ASH) transceiver technology
is specifically designed for short-range wireless data
communication applications. ASH transceivers provide robust
operation, very small size, low power consumption and low
implementation cost. All critical RF functions are contained in the
hybrid, simplifying and speed-ing design-in. ASH transceivers can
be readily configured to support a wide range of data rates and
protocol requirements. These transceivers feature excellent
suppression of transmitter harmonics and virtually no RF
emissions when receiving, making them easy to certify to short-
range (unlicensed) radio regulations.
Amplifier-Sequenced Receiver Operation
The ASH transceiver’s unique feature set is made possible by its
system architecture. The heart of the transceiver is the amplifier-
sequenced receiver section, which provides more than 100 dB of
stable RF and detector gain without any special shielding or
decoupling requirements.
Figure 1 shows the basic block diagram and timing cycle for an
amplifier sequenced receiver. Note that the bias to RF amplifiers
RFA1 and RFA2 are independently controlled by a pulse
generator, and that the two amplifiers are coupled by a surface
acoustic wave (SAW) delay line, which has a typical delay of
0.5 µs.
An incoming RF signal is first filtered by a narrow-band SAW filter,
and is then applied to RFA1. The pulse generator turns RFA1 ON
for 0.814 µs. The amplified signal from RFA1 emerges from the
SAW delay line at the input to RFA2. RFA1 is now switched OFF
and RFA2 is switched ON for 0.814 µs, amplifying the RF signal
further. The ON time for RFA1 and RFA2 is set by a 614 kHz
internal pulse generator. As shown in the timing diagram, RFA1
and RFA2 are never on at the same time, assuring excellent
receiver stability. Note that the narrow-band SAW filter eliminates
sampling sideband responses outside of the receiver passband,
and the SAW filter and delay line act together to provide very high
receiver ultimate rejection.
ASH Transceiver Block Diagram
Figure 2 is the general block diagram of the ASH transceiver.
Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the transceiver are
the antenna and its matching components. Antennas presenting
an impedance in the range of 35 to 72 ohms resistive can be
satisfactorily matched to the RFIO pin with a series matching coil
and a shunt matching/ESD protection coil. Other antenna
impedances can be matched using two or three components. For
some impedances, two inductors and a capacitor will be required.
ASH Receiver Block Diagram & Timing Cycle
Antenna
SAW Filter
RFA1
P1
SAW
Delay Line
RFA2
P2
Detector &
Low-Pass
Filter
Data
Out
Pulse
Generator
RF Input
RF Data Pulse
t
PW1
P1
RFA1 Out
t
PRI
t
PRC
Delay Line
Out
t
PW2
P2
Figure 1
©2010-2015 by Murata Electronics N.A., Inc.
TR7002 (R) 4/23/15
Page 4 of 15
www.murata.com
3G ASH Transceiver Block Diagram
TX
CN
CN CN
MOD TRL1 TRL0 FGR
R
TXM
8
Power Down Control
17
18
19
Programming
and
Control
Baud Rate
Selection
Log
BBOUT
Ref
DS2
dB Below
Peak Thld
Antenna
TXA2
X
TXA1
RFIO
20
ESD
Choke
SAW
CR Filter
RFA1
X
SAW
Delay Line
RFA2
Detector
Low-Pass
Filter
LPFADJ 9
BB
5
C
BBO
6
Peak
Detector
PKDET 4
C
PKD
Temperature
Compensated
Master Oscillator
VCC1:
VCC3:
VCC2:
GND1:
GND2:
Pin 2
Pin 3
Pin 16
Pin 1
Pin 10
AGC Set
Gain Select
Local Oscillator,
Pulse Generator
& RF Amp Bias
15
AND
R
LPF
AGC
Ref
AGC
Control
AGC Reset
13
R
TH1
DS1
Thld
Threshold
Control
THLD1
11
R
REF
12
R
TH2
THLD2
Data/Clock
Recovery 7
14
RXDATA
RXDCLK
Figure 2
A DC path from RFIOto ground is required for ESD protection.
Receiver Chain
The output of the SAW filter drives amplifier RFA1. This amplifier
includes provisions for detecting the onset of saturation (AGC Set),
and for switching between 35 dB of gain and 5 dB of gain (Gain
Select). AGC Set is an input to the AGC Control function, and Gain
Select is the AGC Control function output. ON/OFF control to
RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp
Bias function. The output of RFA1 drives the SAW delay line, which
has a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below
saturation. The output of RFA2 drives a full-wave detector with 19
dB of threshold gain. The onset of saturation in each section of
RFA2 is detected and summed to provide a logarithmic response.
This is added to the output of the full-wave detector to produce an
overall detector response that is square law for low signal levels,
and transitions into a log response for high signal levels. This
combination provides excellent threshold sensitivity and more than
70 dB of detector dynamic range. In combination with the 30 dB of
AGC range in RFA1, more than 100 dB of receiver dynamic range
is achieved.
The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with
excellent group delay flatness and minimal pulse ringing. The 3 dB
bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an
external resistor.
The filter is followed by a base-band amplifier which boosts the
detected signal to the BBOUT pin. When the receiver RF amplifiers
are operating at a 50%-50% duty cycle, the BBOUT signal
changes about 10 mV/dB, with a peak-to-peak signal level of up to
450 mV. For lower duty cycles, the mV/dB slope and peak-to-peak
signal level are proportionately less. The detected signal is riding
©2010-2015 by Murata Electronics N.A., Inc.
TR7002 (R) 4/23/15
on a 1.5 Vdc level that varies somewhat with supply voltage,
temperature, etc. BBOUT is coupled to the CMPIN pin, or to an
external data recovery process (DSP), by a series capacitor. The
correct value of the series capacitor depends on data rate, data run
length, and other factors as discussed in the
ASH Transceiver
Designer’s
Guide.
When an external data recovery process is used with AGC,
BBOUT must be coupled to the external data recovery process
and to CMPIN by separate series coupling capacitors. The AGC
reset function is driven by the signal applied to CMPIN.
Data Slicers
The CMPIN pin drives two data slicers, which convert the analog
signal from BBOUT back into a digital stream. The best data slicer
configuration depends on the system operating parameters. Data
slicer DS1 is a capacitively-coupled comparator with provisions for
an adjustable threshold. DS1 provides the best performance at low
signal-to-noise conditions. The threshold, or squelch, offsets the
comparator’s slicing level from 0 to 90 mV, and is set with a resistor
between the RREF and THLD1 pins. This threshold allows a trade-
off between receiver sensitivity and output noise density in the no-
signal condition. For best sensitivity, the threshold is set to zero but
a minimum R
TH1
value of approximately 20 K Ohms should be
used for proper AGC action. In this case, noise is output
continuously when no signal is present. This, in turn, requires the
circuit being driven by the RXDATA pin to be able to process noise
(and signals) continuously.
This can be a problem if RXDATA is driving a circuit that must
sleep when data is not present to conserve power, or when it its
necessary to minimize false interrupts to a multitasking processor.
In this case, noise can be greatly reduced by increasing the
threshold level, but at the expense of sensitivity. In order to
guarantee THLD1 to be the value calculated, the device should not
be powered up in the receive mode. It should be powered up in
Page 5 of 15
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