CPU to 3V66 Output Offset: ........... 0.0 to1.5 ns (CPU leads)
3V66 to PCI Output Offset:.......... 1.5 to 3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ...... 1.5 to 4.0 ns (CPU leads)
CPU to PCI Output Offset:............. 1.5 to 4.0 ns (CPU leads)
Logic inputs, except SEL133/100#, have 250-k pull-up
resistors
Table 1. Pin Selectable Frequency
[1]
SEL133/100#
1
0
CPU0:3 (MHz)
133 MHz
100 MHz
PCI
33.3 MHz
33.3 MHz
Key Specifications
Supply Voltages: ...................................... V
DDQ3
= 3.3V±5%
Note:
1. See
Table 2
for complete mode selection details.
Block Diagram
X1
X2
CPU_STOP#
Pin Configuration
2
REF0:1
XTAL
OSC
STOP
Clock
Logic
4
CPU0:3
2
SPREAD#
SEL0
SEL1
SEL133/100#
÷2/÷1.5
÷2
CPUdiv2_0:1
PLL 1
STOP
Clock
Logic
4
3V66_0:3
1
PCI_F
STOP
Clock
Logic
7
PCI1:7
PWRDWN#
PCI_STOP#
÷2
Power
Down
Logic
3
÷2
IOAPIC0:2
GND
REF0
REF1
VDDQ3
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
GND
3V66_0
3V66_1
VDDQ3
GND
3V66_2
3V66_3
VDDQ3
SEL133/100#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
IOAPIC2
IOAPIC1
IOAPIC0
GND
VDDQ2
CPUdiv2_1
CPUdiv2_0
GND
VDDQ2
CPU3
CPU2
GND
VDDQ2
CPU1
CPU0
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL1
SEL0
VDDQ3
48MHz
GND
W158
Three-state
Logic
PLL2
1
48MHz
......Document #: 38-07164 Rev. *A Page Page 1 of 12 of 12
400 West Cesar Chavez, Austin, TX 78701
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1+(512) 416-9669
www.silabs.com
W158
Pin Definitions
Pin
Pin No.
Type
Pin Description
41, 42, 45, 46 O
CPU Clock Outputs 0 through 3:
These four CPU clocks run at a frequency set by
SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2.
CPUdiv2_ 0:1
49, 50
O
Synchronous Memory Reference Clock Output 0 through 1:
Reference clock for
Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output voltage
swing is set by the voltage applied to VDDQ2.
PCI1:7
9, 11, 12, 14,
O
PCI Clock Outputs 1 through 7:
These seven PCI clock outputs run synchronously to
15, 17, 18
the CPU clock. Voltage swing is set by the power connection to VDDQ3. PCI1:7 outputs
are stopped when PCI _STOP# is held LOW.
PCI_F
8
O
PCI_F (PCI Free-running):
This PCI clock output runs synchronously to the CPU clock.
Voltage swing is set by the power connection to VDDQ3. PCI_F is not affected by the
state of PCI_STOP#.
REF0:1
2, 3
O
14.318-MHz Reference Clock Output:
3.3V copies of the 14.318-MHz reference clock.
IOAPIC0:2
53, 54, 55
O
I/O APIC Clock Output:
Provides 16.67-MHz fixed frequency. The output voltage swing
is set by the power connection to VDDQ2.
48MHz
30
O
48-MHz Output:
Fixed 48-MHz USB output. Output voltage swing is controlled by voltage
applied to VDDQ3.
3V66_0:3
21, 22, 25, 26 O
66-MHz Output 0 through 3:
Fixed 66-MHz outputs. Output voltage swing is controlled
by voltage applied to VDDQ3.
SEL0:1
32, 33
I
Mode Select Input 0 through 1:
3.3V LVTTL-compatible input for selecting clock output
modes.
SEL133/100#
28
I
Frequency Selection Input:
3.3V LVTTL-compatible input that selects CPU output
frequency as shown in
Table 1.
X1
5
I
Crystal Connection or External Reference Frequency Input:
Connect to either a
14.318-MHz crystal or an external reference signal.
X2
6
O
Crystal Connection:
An output connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
SPREAD#
34
I
Active LOW Spread Spectrum Enable:
3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
PWRDWN#
35
I
Active LOW Power Down Input:
3.3V LVTTL-compatible asynchronous input that
requests the device to enter power-down mode.
Active LOW CPU Clock Stop:
3.3V LVTTL-compatible asynchronous input that stops all
CPU_STOP#
36
I
CPU and 3V66 clocks when held LOW. CPUdiv2 outputs are unaffected by this input.
PCI_STOP#
37
I
Active LOW PCI Clock Stop:
3.3V LVTTL-compatible asynchronous input that stops all
PCI outputs except PCI_F when held LOW.
VDDQ3
4, 10, 16, 23,
Power Connection:
Power supply for PCI output buffers, 48-MHz USB output buffer,
P
27, 31, 39
Reference output buffers, 3V66 output buffers, core logic, and PLL circuitry. Connect to
3.3V supply.
VDDQ2
43, 47, 51, 56
P
Power Connection:
Power supply for IOAPIC, CPU, and CPUdiv2 output buffers.
Connect to 2.5V supply.
G
Ground Connection:
Connect all ground pins to the common system ground plane.
GND
1, 7, 13, 19,
20, 24, 29, 38,
40, 44, 48, 52
Pin Name
CPU0:3
Overview
The W158 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel archi-
tecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W158 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also
provides skew-controlled PCI and IOAPIC clocks
synchronous to CPU clock, 48-MHz Universal Serial Bus
(USB) clock, and replicates the 14.31818-MHz reference
clock.
All CPU, PCI, and IOAPIC clocks can be synchronously
modulated for spread spectrum operations. Cypress employs
proprietary techniques that provide the maximum EMI
reduction while minimizing the clock skews that could reduce
system timing margins. Spread Spectrum modulation is
enabled by the active LOW control signal SPREAD#.
The W158 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
..... Document #: 38-07164 Rev. *A Page Page 2 of 12 of 12
W158
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the ampli-
tudes of the radiated electromagnetic emissions are reduced.
This effect is depicted in
Figure 1.
As shown in
Figure 1,
a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 2.
This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% downspread.
Figure
2
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
90%
10%
20%
30%
40%
50%
60%
70%
80%
100%
90%
Time
Figure 2. Modulation Waveform Profile
..... Document #: 38-07164 Rev. *A Page Page 3 of 12 of 12
100%
W158
Mode Selection Functions
The W158 supports the following operating modes controlled through the SEL133/100#, SEL0, and SEL1 inputs.
Table 2. Select Functions
SEL133/100#
0
0
0
0
1
1
1
1
Table 3. Truth Table
SEL
133/100#
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
HI-Z
n/a
100 MHz
100 MHz
TCLK/2
n/a
133 MHz
133 MHz
CPUdiv2
HI-Z
n/a
50 MHz
50 MHz
TCLK/4
n/a
66 MHz
66 MHz
3V66
HI-Z
n/a
66 MHz
66 MHz
TCLK/4
n/a
66 MHz
66 MHz
PCI
HI-Z
n/a
33 MHz
33 MHz
TCLK/8
n/a
33 MHz
33 MHz
48MHz
HI-Z
n/a
HI-Z
48 MHz
TCLK/2
n/a
HI-Z
48 MHz
REF
HI-Z
n/a
IOAPIC
HI-Z
n/a
3
4, 7, 8
5, 6
3
4, 7, 8
Notes
2
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
(Reserved)
Active 100-MHz, 48-MHz PLL Inactive
Active 100-MHz, 48-MHz PLL Active
Test Mode
(Reserved)
Active 133-MHz, 48-MHz PLL Inactive
Active 133-MHz, 48-MHz PLL Active
Function
All Outputs Three-State
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
TCLK
n/a
TCLK16
n/a
14.318 MHz 16.67 MHz
14.318 MHz 16.67 MHz
Table 4. Maximum Supply Current
Max. 2.5V supply consumption
Max. discrete cap loads,
V
DDQ2
=2.625V
All static inputs=V
DDQ3
or GND
100 µA
75 mA
Max. 3.3V supply consumption
Max. discrete cap loads,
V
DDQ3
=3.465V or GND
200 µA
160 mA
Condition
Powerdown Mode
(PWRDWN#=0)
Full Active 100 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
Full Active 133 MHz
SEL133/100#=0
SEL1, 0=11
CPU_STOP#, PCI_STOP#=1
90 mA
160 mA
Notes:
2. Provided for board level “bed of nails” testing.
3. 48-MHz PLL disabled to reduce component jitter.
4. Normal” mode of operation.
5. TCLK is a test clock over driven on the X1 input during test mode. TCLK mode is based on 133-MHz CPU select logic.
6. Required for DC output impedance verification.
7. Range of reference frequency is min.=14.316, nominal = 14.31818 MHz, max.=14.32 MHz.
8. Frequency accuracy of 48 MHz is +167 PPM to match USB default.
..... Document #: 38-07164 Rev. *A Page Page 4 of 12 of 12
W158
Table 5. Clock Enable Configuration
[9, 10, 11, 12, 13, 14]
CPU_STOP# PWRDWN# PCI_STOP#
X
0
0
1
1
0
1
1
1
1
X
0
1
0
1
CPU
LOW
LOW
LOW
ON
ON
CPUdiv2 IOAPIC
LOW
ON
ON
ON
ON
LOW
ON
ON
ON
ON
3V66
LOW
LOW
LOW
ON
ON
PCI
LOW
LOW
ON
LOW
ON
PCI_F
LOW
ON
ON
ON
ON
REF,
48MHz
LOW
ON
ON
ON
ON
OSC.
OFF
ON
ON
ON
ON
VCOs
OFF
ON
ON
ON
ON
Table 6. Power Management State Transition
[15, 16]
Latency
Signal
CPU_STOP#
PCI_STOP#
PWRDWN#
Signal State
0 (disabled)
1 (enabled)
0 (disabled)
1 (enabled)
1 (normal operation)
0 (power down)
No. of rising edges of PCI Clock
1
1
1
1
3 ms
2 max.
Timing Diagrams
CPU_STOP# Timing Diagram
[17, 18, 19, 20, 21, 22]
CPU
(internal)
PCI
CPU_STOP#
PCI_STOP#
PWRDWN#
HI
HI
CPU
(external)
3V66
Notes:
9. LOW means outputs held static LOW as per latency requirement below.
10. ON means active.
11. PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
12. All 3V66 as well as all CPU clocks stop cleanly when CPU_STOP# is pulled LOW.
13. CPUdiv2, IOAPIC, REF, 48MHz signals are not controlled by the CPU_STOP# functionality and are enabled in all conditions except PWRDWN#=LOW.
14. An “x” indicates a “don’t care” condition.
15. Clock on/off latency is defined in the number of rising edges of the free-running PCI clock between when the clock disable goes LOW/HIGH to when the first valid
clock comes out of the device.
16. Power up latency is from when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
17. All internal timing is referenced to the CPU clock.
18. The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
19. CPU_STOP# signal is an input signal that must be made synchronous to free-running PCI_F.
20. 3V66 clocks also stop/start before.
21. PWRDWN# and PCI_STOP# are shown in a HIGH state.
22. Diagrams shown with respect to 133 MHz. Similar operation when CPU clock is 100 MHz.
..... Document #: 38-07164 Rev. *A Page Page 5 of 12 of 12
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