INTEGRATED CIRCUITS
74ABT16374B
16-bit D-type flip-flop;
positive-edge trigger (3-State)
Product data
Supersedes data of 2004 Mar 01
2004 Mar 08
Philips
Semiconductors
Philips Semiconductors
Product data
16-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT16374B
DESCRIPTION
The 74ABT16374B high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16374B has two 8-bit, edge triggered registers, with each
register coupled to eight 3-State output buffers. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. Each
active-LOW Output Enable (nOE) controls all eight 3-State buffers
for its register independent of the clock operation.
When nOE is LOW, the stored data appears at the outputs for that
register. When nOE is HIGH, the outputs for that register are in the
high-impedance “OFF” state, which means they will neither drive nor
load the bus.
FEATURES
•
Two 8-bit positive edge triggered registers
•
Live insertion/extraction permitted
•
Power-up 3-State
•
Power-up reset
•
Multiple V
CC
and GND pins minimize switching noise
•
3-State output buffers
•
Output capability: +64 mA/–32 mA
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
I
CCL
Propagation delay
nCP to nQx
Input capacitance
Output capacitance
Quiescent supply current
PARAMETER
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 50 pF; V
CC
= 5 V
V
I
= 0 V or V
CC
V
O
= 0V or V
CC
; 3-State
Outputs disabled; V
CC
= 5.5 V
Outputs LOW; V
CC
= 5.5 V
TYPICAL
2.6
2.2
4
7
500
8
UNIT
ns
pF
pF
µA
mA
ORDERING INFORMATION
T
amb
= –40
°
C to +85
°
C
Type number
Package
Name
74ABT16374BB
74ABT16374BDGG
74ABT16374BDL
QFP52
TSSOP48
SSOP48
Description
plastic quad flat package; 52 leads (lead length 1.6 mm); body 10
×
10
×
2.0 mm
plastic thin shrink small outline package; 48 leads; body width 6.1 mm
plastic shrink small outline package; 48 leads; body width 7.5 mm
Version
SOT379-1
SOT362-1
SOT370-1
2004 Mar 08
2
Philips Semiconductors
Product data
16-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT16374B
PIN CONFIGURATION
TSSOP48 and SSOP48 pinning
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1CP
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
2Q4 14
2Q5 15
GND 16
2Q6 17
2Q7 18
2OE 19
GND 20
2CP 21
2D7 22
2D6 23
GND 24
2D5 25
V
CC
2D4
2D5
GND
2D6
2D7
2CP
2D4 26
V
CC
1Q4
1Q5
GND
1Q6
1Q7
GND
2Q0
2Q1
1
2
3
4
5
6
7
8
9
QFP52 pinning
50 GND
46 GND
52 1Q3
42 GND
47 1OE
45 1CP
51 1Q2
49 1Q1
48 1Q0
44 1D0
43 1D1
41 1D2
40 1D3
39
38
37
36
35
34
V
CC
1D4
1D5
GND
1D6
1D7
GND
2D0
2D1
GND
2D2
2D3
V
CC
74ABT16374BB
QFP52
33
32
31
30
29
28
27
GND 10
2Q2 11
2Q3 12
V
CC
13
SW02219
SA00326
PIN DESCRIPTION
PIN NUMBER
SYMBOL
TSSOP and SSOP
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
1, 24
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
QFP52
44, 43, 41, 40, 38, 37, 35, 34
32, 31, 29, 28, 26, 25, 23, 22
48, 49, 51, 52, 2, 3, 5, 6
8, 9, 11, 12, 14, 15, 17, 18
47, 19
45, 21
4, 7, 10, 16, 20, 24, 30, 33,
36, 42, 46, 50
1, 13, 27, 39
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
1CP, 2CP
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active-LOW)
Clock pulse inputs (active rising edge)
Ground (0 V)
Positive supply voltage
FUNCTION
2004 Mar 08
3
Philips Semiconductors
Product data
16-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT16374B
LOGIC SYMBOL
47
46
44
43
41
40
38
37
LOGIC SYMBOL (IEEE/IEC)
1OE
1CP
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2D
2
∇
1EN
C1
2EN
C2
1D
1
∇
2 1Q0
3 1Q1
5 1Q2
6 1Q3
8 1Q4
9 1Q5
11 1Q6
12 1Q7
13 2Q0
14 2Q1
16
2Q2
17
2Q3
19
2Q4
20
2Q5
22
2Q6
23
2Q7
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1CP
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2OE
2CP
1D0
1D1
1D2
2
36
3
35
5
33
6
32
8
30
9
29
11
27
12
26
1D3
1D4
1D5
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2CP
1D6
1D7
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D0
2D1
2D2
13
14
16
17
19
20
22
23
2D3
2D4
2D5
2D6
2D7
SH00078
SH00077
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
nCP
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00327
FUNCTION TABLE
INPUTS
nOE
L
L
L
nCP
↑
↑
↑
nDx
l
h
X
INTERNAL
REGISTER
L
H
NC
OUTPUTS
nQ0 – nQ7
L
H
NC
OPERATING MODE
Load and read register
Hold
Disable outputs
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
H
↑
X
NC
Z
H
↑
nDx
nDx
Z
HIGH voltage level
HiIGH voltage level one set-up time prior to the HIGH-to-LOW E transition
LOW voltage level
LOW voltage level one set-up time prior to the HIGH-to-LOW E transition
No change
Don’t care
High-impedance “off” state
LOW-to-HIGH clock transition
Not a LOW-to-HIGH clock transition
4
2004 Mar 08
Philips Semiconductors
Product data
16-bit D-type flip-flop; positive-edge trigger
(3-State)
74ABT16374B
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
output in HIGH state
Storage temperature range
–64
–65 to 150
mA
°C
V
O
< 0 V
output in Off or HIGH state
output in LOW state
V
I
< 0 V
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
UNIT
V
mA
V
mA
V
mA
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
Input transition rise or fall rate
Operating free-air temperature range
PARAMETER
MIN
4.5
0
2.0
–
–
–
0
–40
MAX
5.5
V
CC
–
0.8
–32
64
10
+85
UNIT
V
V
V
V
mA
mA
ns/V
°C
2004 Mar 08
5
嵌入式系统
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