74F164A Serial-In, Parallel-Out Shift Register
October 1989
Revised October 2000
74F164A
Serial-In, Parallel-Out Shift Register
General Description
The 74F164A is a high-speed 8-bit serial-in/parallel-out
shift register. Serial data is entered through a 2-input AND
gate synchronous with the LOW-to-HIGH transition of the
clock. The device features an asynchronous Master Reset
which clears the register, setting all outputs LOW indepen-
dent of the clock. The 74F164A is a faster version of the
74F164.
Features
s
Typical shift frequency of 90 MHz
s
Asynchronous Master Reset
s
Gated serial data input
s
Fully synchronous data transfers
s
74F164A is a faster version of the 74F164
Ordering Code:
Order Number
74F164ASC
74F164ASJ
74F164APC
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS010613
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74F164A
Unit Loading/Fan Out
Pin Names
A, B
CP
MR
Q
0
–Q
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
Description
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
Functional Description
The 74F164A is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
HIGH Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the log-
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Mode Select Table
Operating
Mode
Reset (Clear)
Shift
MR
L
H
H
H
H
Inputs
A
X
l
l
h
h
B
X
l
h
l
h
Outputs
Q
0
L
L
L
L
H
Q
1
–Q
7
L-L
q
0
–q
6
q
0
–q
6
q
0
–q
6
q
0
–q
6
H(h)
=
HIGH Voltage Levels
L(l)
=
LOW Voltage Levels
X
=
Immaterial
q
n
=
Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F164A
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 1)
Input Current (Note 1)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
35
4.75
3.75
−0.6
−150
55
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All other pins grounded
V
IOD
=
150 mV
All other pins grounded
V
IN
=
0.5V
V
OUT
=
0V
CP
=
HIGH
MR
=
GND, A, B
=
GND
3
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74F164A
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PHL
Maximum Clock Frequency
Propagation Delay
CP to Q
n
Propagation Delay
MR to Q
n
80
3.0
3.5
5.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
120
4.8
5.0
7.0
7.5
8.0
10.0
Max
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
C
L
=
50 pF
Min
60
2.5
3.0
4.0
9.0
8.5
12.5
Max
T
A
=
0°C to
+70°C
V
CC
=
5.0V
C
L
=
50 pF
Min
80
3.0
3.5
5.0
7.5
8.0
10.5
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
A or B to CP
Hold Time, HIGH or LOW
A or B to CP
CP Pulse Width
HIGH or LOW
MR Pulse Width, LOW
Recovery Time
MR to CP
4.5
4.0
1.0
1.0
4.0
7.0
4.0
5.0
Max
T
A
= −55°C
to
+125°C
V
CC
=
5.0V
Min
5.5
4.0
1.0
1.0
4.0
7.0
5.0
6.5
Max
T
A
=
0°C to
+70°C
V
CC
=
5.0V
Min
4.5
4.0
1.0
1.0
4.0
7.0
4.0
5.0
ns
ns
ns
ns
Max
Units
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4
74F164A
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
5
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