73S1217F
Bus-Powered
80515 System-on-Chip with USB,
ISO 7816 / EMV, PINpad and More
Simplifying System Integration™
DATA SHEET
December 2008
GENERAL DESCRIPTION
The Teridian Semiconductor Corporation 73S1217F is a
versatile and economical CMOS System-on-Chip device
intended for smart card reader applications. The circuit
features an ISO-7816 / EMV interface, an USB 2.0
interface (full-speed 12Mbps - slave) and a 5x6 PINpad
interface. Additional features include 8 user I/Os,
multiple interrupt options and an analog voltage input (for
DC voltage monitoring such as battery level detection).
Other built-in interfaces include an asynchronous serial
and an I
2
C interface.
The System-on-Chip is built around an 80515 high-
performance core. Its feature and instruction set is
compatible with the industry standard 8051, while
offering one clock-cycle per instruction processing
power (most instructions). With a CPU clock running up
to 24MHz, it results in up to 20MIPS available that
meets the requirements of various encryption needs
such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance). The circuit requires a single 6
to 12 MHz crystal. An optional 32kHz crystal can be
connected to a sub-system oscillator with a real-time-
clock counter to enable stand-alone applications to
access an RTC value.
The respective 73S1217F embedded memories are;
64KB Flash program memory, 2KB user XRAM
memory, and 256B IRAM memory. On top of these
memories are added independent FIFOs dedicated to
the ISO7816 UART and to the USB interface.
The chip incorporates an inductor-based DC-DC
converter that generates all the necessary voltages to
the various 73S1217F function blocks (smart card
interface, digital core, etc.) from any of two distinct
power supply sources: The +5V USB bus (V
BUS
, 4.4V to
6.5V), or a main battery (V
BAT
, 4.0V to 6.5V). The chip
automatically powers-up the DC-DC converter with V
BUS
if it is present, or uses V
BAT
as the supply input.
Alternatively, the pin V
PC
can support a wider power
supply input range (2.7V to 6.5V), when using a single
system supply source.
In addition, the circuit features an ON/OFF mode which
operates directly with an ON/OFF system switch: Any
activity on the ON/OFF button is debounced internally
and controls the power generation circuit accordingly,
under the supervision of the firmware (OFF request /
OFF acknowledgement at firmware level). The OFF
mode can be alternatively initiated from the controller
(firmware action instead of ON/OFF switch).
In OFF mode, the circuit typically draws less than 1μA,
which makes it ideal for applications where battery life
must be maximized.
Wake-up of the controller upon USB cable insertion is
supported.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the Teridian 73S1217F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1217F a very comprehensive set of software libraries,
including the smart card and USB protocol layers that are
pre-approved against USB, Microsoft WHQL and EMV,
as well as a CCID reference design. Refer to the
Teridian Semiconductor Corporation
73S12xxF Software
User’s Guide
for a complete description of the Application
Programming Interface (API Libraries) and related
Software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable
rapid development and certification of readers that
meet most demanding smart card standards.
APPLICATIONS
•
•
•
•
•
Hand-held PINpad smart card readers:
With USB or serial connectivity
Ideal for E-banking (MasterCard CAP, etc) and Digital
Identification (Secure Login, Gov’t ID...)
Transparent USB card readers and USB keys
General purpose smart card readers
ADVANTAGES
•
•
•
•
•
•
•
•
Reduced BOM
Larger built-in Flash / RAM than its competitors
Higher performance CPU core (up to 24MIPS)
On-chip DC-DC converter and CMOS switches for
battery and USB power
Sub-μA Power Down mode with ON/OFF switch
Powerful In-Circuit Emulation and Programming
A
complete set of EMV4.1, USB and CCID libraries
Overall, the ideal compromise cost / features for high
volume, PINpad reader applications!
Rev. 1.2
© 2008 Teridian Semiconductor Corporation
1
73S1217F Data Sheet
DS_1217F_001
FEATURES
80515 Core:
•
•
•
•
•
•
1 clock cycle per instruction (most instructions)
CPU clocked up to 24MHz
64kB Flash memory (lockable)
2kB XRAM (User Data Memory)
256 byte IRAM
Hardware watchdog timer
Communication Interfaces:
•
•
•
•
•
•
•
Full-duplex serial interface (1200 to 115kbps UART)
USB 2.0 Full Speed 12Mbps Interface, PC/SC
compliant with 4 Endpoints:
Control (16B FIFO)
Interrupt IN (32B FIFO)
Bulk IN (128B FIFO)
Bulk OUT (128B FIFO)
2
I C Master Interface (400kbps)
Oscillators:
•
•
•
Single low-cost 6MHz to 12MHz crystal
Optional 32kHz crystal (with internal RTC)
An Internal PLL provides all the necessary clocks to
each block of the system
Man-Machine Interface and I/Os:
•
•
•
6x5 Keyboard (hardware scanning, debouncing and
scrambling)
(8) User I/Os
Single programmable current output (LED)
Interrupts:
•
•
Standard 80C515 4-priority level structure
9 different sources of interrupt to the core
Voltage Detection:
•
Analog Input (detection range: 1.0V to 1.5V)
Power Down Modes:
•
•
2 standard 80C515 Power Down and IDLE modes
Sub-μA OFF mode
Operating Voltage:
•
•
•
Single supply 2.7V to 6.5V operation (VPC)
USB supply (VBUS 4.4V to 5.5V) with or without
battery back up operation (VBAT 4.0V to 6.5V).
Automated detection of voltage presence - Priority on
VBUS over VBAT
ON/OFF Main System Power Switch:
•
Input for an SPST momentary switch to ground
Timers:
•
•
(2) Standard 80C52 timers T0 and T1
(1) 16-bit timer that can generate RTC interrupts
from the 32kHz clock
DC-DC Converter:
•
•
•
•
Step-up converter
Generates an intermediary voltage VP
Requires a single 10μH Inductor
3.3V supply available for external circuits
Built-in ISO-7816 Card Interface:
•
•
•
•
•
•
LDO regulator produces VCC for the card
(1.8V, 3V or 5V)
Full compliance with EMV 4.1
Activation/Deactivation sequencers
Auxiliary I/O lines (C4-C8 signals)
7kV ESD protection on all interface pins
Operating Temperature:
•
-40°C to 85°C
Package:
•
68-pin QFN
Software:
•
•
•
Two-level Application Programming Interface
(ANSI C-language libraries)
USB, T=0 / T=1 ISO and EMV compliant smart card
protocol layers
®
CCID reference design and Windows driver
Communication with Smart Cards:
•
•
•
ISO 7816 UART for T=0, T=1
(2) 2-Byte FIFOs for transmit and receive
Configured to drive multiple external Teridian
73S8010xx interfaces (for multi-SAM architectures)
2
Rev. 1.2
DS_1217F_002
73S1217F Data Sheet
Table of Contents
1
Hardware Description ......................................................................................................................... 8
1.1
Pin Description .............................................................................................................................. 8
1.2
Hardware Overview .................................................................................................................... 11
1.3
80515 MPU Core ........................................................................................................................ 11
1.3.1
80515 Overview ............................................................................................................. 11
1.3.2
Memory Organization .................................................................................................... 11
1.4
Program Security ........................................................................................................................ 16
1.5
Special Function Registers (SFRs) ............................................................................................ 18
1.5.1
Internal Data Special Function Registers (SFRs).......................................................... 18
1.5.2
IRAM Special Function Registers (Generic 80515 SFRs) ............................................ 19
1.5.3
External Data Special Function Registers (SFRs) ........................................................ 20
1.6
Instruction Set ............................................................................................................................. 23
1.7
Peripheral Descriptions............................................................................................................... 23
1.7.1
Oscillator and Clock Generation .................................................................................... 23
1.7.2
Power Supply Management .......................................................................................... 26
1.7.3
Power ON/OFF .............................................................................................................. 27
1.7.4
Power Control Modes .................................................................................................... 28
1.7.5
Interrupts ........................................................................................................................ 35
1.7.6
UART ............................................................................................................................. 42
1.7.7
Timers and Counters ..................................................................................................... 47
1.7.8
WD Timer (Software Watchdog Timer) ......................................................................... 49
1.7.9
User (USR) Ports ........................................................................................................... 52
1.7.10
Real-Time Clock with Hardware Watchdog (RTC) ........................................................ 54
1.7.11
Analog Voltage Comparator .......................................................................................... 57
1.7.12
LED Driver ..................................................................................................................... 59
1.7.13
I
2
C Master Interface ....................................................................................................... 60
1.7.14
Keypad Interface ............................................................................................................ 67
1.7.15
Emulator Port ................................................................................................................. 74
1.7.16
USB Interface ................................................................................................................ 75
1.7.17
Smart Card Interface Function ...................................................................................... 78
1.7.18
VDD Fault Detect Function .......................................................................................... 113
Application Schematics ................................................................................................................. 114
2.1
Typical Application Schematic 1 ............................................................................................... 114
2.2
Typical Application Schematic 2 ............................................................................................... 115
Electrical Specification................................................................................................................... 116
3.1
Absolute Maximum Ratings ...................................................................................................... 116
3.2
Recommended Operating Conditions ...................................................................................... 116
3.3
Digital IO Characteristics .......................................................................................................... 117
3.4
Oscillator Interface Requirements ............................................................................................ 118
3.5
DC Characteristics: Analog Input ............................................................................................. 118
3.6
USB Interface Requirements .................................................................................................... 119
3.7
Smart Card Interface Requirements ......................................................................................... 121
3.8
DC Characteristics .................................................................................................................... 123
3.9
Current Fault Detection Circuits ............................................................................................... 125
Equivalent Circuits ......................................................................................................................... 126
4.1
Package Pin Designation (68-Pin QFN) ................................................................................... 135
4.2
Packaging Information .............................................................................................................. 136
Ordering Information ...................................................................................................................... 137
Related Documentation .................................................................................................................. 137
Contact Information ........................................................................................................................ 137
2
3
4
5
6
7
Revision History ...................................................................................................................................... 138
Rev. 1.2
3
73S1217F Data Sheet
DS_1217F_002
Figures
Figure 1: IC Functional Block Diagram ......................................................................................................... 7
Figure 2: Memory Map ................................................................................................................................ 15
Figure 3: Clock Generation and Control Circuits ........................................................................................ 23
Figure 4: Oscillator Circuit ........................................................................................................................... 25
Figure 5: Detailed Power Management Logic Block Diagram .................................................................... 26
Figure 6: Power-Down Control.................................................................................................................... 29
Figure 7: Detail of Power-Down Interrupt Logic .......................................................................................... 30
Figure 8: Power-Down Sequencing ............................................................................................................ 30
Figure 9: External Interrupt Configuration ................................................................................................... 35
Figure 10: Real Time Clock Block Diagram ................................................................................................ 54
Figure 11: I
2
C Write Mode Operation .......................................................................................................... 61
Figure 12: I
2
C Read Operation ................................................................................................................... 62
Figure 13: Simplified Keypad Block Diagram ............................................................................................. 67
Figure 14: Keypad Interface Flow Chart ..................................................................................................... 69
Figure 15: USB Block Diagram ................................................................................................................... 75
Figure 16: Smart Card Interface Block Diagram ......................................................................................... 78
Figure 17: Smart Card Interface Block Diagram ......................................................................................... 79
Figure 18: Asynchronous Activation Sequence Timing .............................................................................. 81
Figure 19: Deactivation Sequence .............................................................................................................. 82
Figure 20: Smart Card CLK and ETU Generation ...................................................................................... 83
Figure 21: Guard, Block, Wait and ATR Time Definitions .......................................................................... 84
Figure 22: Synchronous Activation ............................................................................................................. 86
Figure 23: Example of Sync Mode Operation: Generating/Reading ATR Signals ..................................... 86
Figure 24: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode ................................. 87
Figure 25: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode ................................. 87
Figure 26: Operation of 9-bit Mode in Sync Mode ...................................................................................... 88
Figure 27: 73S1217F Typical Application Schematic (Handheld USB PINpad, with Combo USB-
Bus and Self-powered Configuration) ..................................................................................... 114
Figure 28: 73S1217F Typical Application Schematic (USB Transparent Reader and USB Key
Configuration) .......................................................................................................................... 115
Figure 29: 12 MHz Oscillator Circuit ......................................................................................................... 126
Figure 30: 32KHz Oscillator Circuit ........................................................................................................... 126
Figure 31: Digital I/O Circuit ...................................................................................................................... 127
Figure 32: Digital Output Circuit ................................................................................................................ 127
Figure 33: Digital I/O with Pull Up Circuit .................................................................................................. 128
Figure 34: Digital I/O with Pull Down Circuit ............................................................................................. 128
Figure 35: Digital Input Circuit ................................................................................................................... 129
Figure 36: OFF_REQ Interface Circuit ..................................................................................................... 129
Figure 37: Keypad Row Circuit ................................................................................................................. 130
Figure 38: Keypad Column Circuit ............................................................................................................ 130
Figure 39: LED Circuit ............................................................................................................................... 131
Figure 40: Test and Security Pin Circuit ................................................................................................... 131
Figure 41: Analog Input Circuit ................................................................................................................. 132
Figure 42: Smart Card Output Circuit ....................................................................................................... 132
Figure 43: Smart Card I/O Circuit ............................................................................................................. 133
Figure 44: PRES Input Circuit ................................................................................................................... 133
Figure 45: USB Circuit .............................................................................................................................. 134
Figure 46: ON_OFF Input Circuit .............................................................................................................. 134
Figure 47: 73S1217F Pinout ..................................................................................................................... 135
Figure 48: 73S1217F 68 QFN Mechanical Drawing ................................................................................. 136
4
Rev. 1.2
DS_1217F_002
73S1217F Data Sheet
Tables
Table 1: 73S1217 Pinout Description ........................................................................................................... 8
Table 2: MPU Data Memory Map ............................................................................................................... 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................ 18
Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register Flags ...................................................................................................................... 22
Table 10: Port Registers ............................................................................................................................. 22
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 24
Table 12: The MCLKCtl Register ................................................................................................................ 24
Table 13: The MPUCKCtl Register ............................................................................................................. 25
Table 14: The INT5Ctl Register .................................................................................................................. 31
Table 15: The MISCtl0 Register.................................................................................................................. 31
Table 16: The MISCtl1 Register.................................................................................................................. 32
Table 17: The MCLKCtl Register ................................................................................................................ 33
Table 18: The PCON Register .................................................................................................................... 34
Table 19: The IEN0 Register ...................................................................................................................... 36
Table 20: The IEN1 Register ...................................................................................................................... 37
Table 21: The IEN2 Register ...................................................................................................................... 37
Table 22: The TCON Register .................................................................................................................... 38
Table 23: The T2CON Register .................................................................................................................. 38
Table 24: The IRCON Register ................................................................................................................... 39
Table 25: External MPU Interrupts.............................................................................................................. 39
Table 26: Control Bits for External Interrupts .............................................................................................. 40
Table 27: Priority Level Groups .................................................................................................................. 40
Table 28: The IP0 Register ......................................................................................................................... 40
Table 29: The IP1 Register ......................................................................................................................... 41
Table 30: Priority Levels.............................................................................................................................. 41
Table 31: Interrupt Polling Sequence.......................................................................................................... 41
Table 32: Interrupt Vectors ......................................................................................................................... 41
Table 33: UART Modes .............................................................................................................................. 42
Table 34: Baud Rate Generation ................................................................................................................ 42
Table 35: The PCON Register .................................................................................................................... 43
Table 36: The BRCON Register ................................................................................................................. 43
Table 37: The MISCtl0 Register.................................................................................................................. 44
Table 38: The S0CON Register .................................................................................................................. 45
Table 39: The S1CON Register .................................................................................................................. 46
Table 40: The TMOD Register .................................................................................................................... 47
Table 41: Timers/Counters Mode Description ............................................................................................ 48
Table 42: The TCON Register .................................................................................................................... 49
Table 43: The IEN0 Register ...................................................................................................................... 50
Table 44: The IEN1 Register ...................................................................................................................... 50
Table 45: The IP0 Register ......................................................................................................................... 51
Table 46: The WDTREL Register ............................................................................................................... 51
Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 52
Table 48: UDIR Control Bit ......................................................................................................................... 52
Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 52
Table 50: The USRIntCtl1 Register ............................................................................................................ 53
Table 51: The USRIntCtl2 Register ............................................................................................................ 53
Table 52: The USRIntCtl3 Register ............................................................................................................ 53
Table 53: The USRIntCtl4 Register ............................................................................................................ 53
Table 54: The RTCCtl Register................................................................................................................... 55
Table 55: The 32-bit RTC Counter.............................................................................................................. 56
Table 56: The 24-bit RTC Accumulator ...................................................................................................... 56
Table 57: The 24-bit RTC Trim (sign magnitude value) ............................................................................. 56
Rev. 1.2
5
机器人开发
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
