MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High−Performance Silicon−Gate CMOS
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The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pull−up
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3−state memory address drivers, clock
drivers, and other bus−oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active−low output enables.
The HC540A is similar in function to the HC541A, which has
noninverting outputs.
Features
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
V
CC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
20 19 18 17 16 15 14 13 12 11
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 124 FETs or 31 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
2
3
4
5
6
7
8
9
1
19
PIN 20 = V
CC
PIN 10 = GND
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
20−Lead
(Top View)
MARKING DIAGRAMS
20
74HC540A
AWLYYWWG
1
SOIC−20
A
WL, L
YY, Y
WW, W
G or
G
1
TSSOP−20
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
20
HC
540A
ALYWG
G
A1
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Inverting
Outputs
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
H
L
Z
Z
Output Y
Z = High Impedance
X = Don’t Care
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 11
Publication Order Number:
MC74HC540A/D
MC74HC540A
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage (Note 1)
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 85_C (Note 5)
SOIC
TSSOP
SOIC
TSSOP
Parameter
Value
−0.5 to +7.0
−0.5 to V
CC
+ 0.5
−0.5
≤
V
O
≤
V
CC
+ 0.5
±20
±35
±35
±75
±75
−65 to +150
260
+150
96
128
500
450
Level 1
UL 94 V0 @ 0.125 in
> 2000
> 200
> 1000
±300
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
I
LATCHUP
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Parameter
(Referenced to GND)
(Referenced to GND)
Min
2.0
0
−55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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2
MC74HC540A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
out
= 0.1 V
|I
out
|
≤
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
3.6 mA
|I
out
|
≤
6.0 mA
|I
out
|
≤
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
3.6 mA
|I
out
|
≤
6.0 mA
|I
out
|
≤
7.8 mA
3.0
4.5
6.0
6.0
6.0
−55 to
25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
±10.0
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IL
|I
out
|
≤
20
mA
V
in
= V
IL
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
|
≤
20
mA
V
in
= V
IH
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4
40
160
mA
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−55 to
25°C
80
30
18
15
110
45
25
21
110
45
25
21
60
22
12
10
10
15
≤85°C
100
40
23
20
140
60
31
26
140
60
31
26
75
28
15
13
10
15
≤125°C
120
55
28
25
165
75
38
31
165
75
38
31
90
34
18
15
10
15
Unit
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 5)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 2 and 4)
ns
C
in
C
out
Maximum Input Capacitance
Maximum 3−State Output Capacitance (Output in High Impedance State)
pF
pF
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer) (Note 7)
7. Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
35
pF
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3
MC74HC540A
t
r
90%
INPUT A
t
PHL
90%
OUTPUT Y
t
THL
50%
10%
50%
10%
t
f
V
CC
OE1 or OE2
50%
t
PZL
GND
t
PLH
t
PZH
50%
t
TLH
OUTPUT Y
OUTPUT Y
50%
t
PLZ
V
CC
50%
GND
HIGH
IMPEDANCE
10%
t
PHZ
90%
V
OH
HIGH
IMPEDANCE
V
OL
Figure 2. Switching Waveform
Figure 3. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
and t
PZH
.
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4. Test Circuit
Figure 5. Test Circuit
To 7 Other Inverters
One of Eight
Inverters
INPUT A
V
CC
OUTPUT Y
OE1
OE2
Figure 6. Logic Detail
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MC74HC540A
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in inverted form
on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
OE1, OE2 (PINS 1, 19)
device functions as an inverter. When a high voltage is
applied to either input, the outputs assume the high
impedance state.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11)
Output enables (active−low). When a low voltage is
applied to both of these pins, the outputs are enabled and the
Device outputs. Depending upon the state of the output
enable pins, these outputs are either inverting outputs or
high−impedance outputs.
ORDERING INFORMATION
Device
MC74HC540ADWG
MC74HC540ADWR2G
MC74HC540ADTR2G
NLV74HC540ADTR2G*
Package
SOIC−20 WIDE
(Pb−Free)
SOIC−20 WIDE
(Pb−Free)
TSSOP−20
(Pb−Free)
TSSOP−20
(Pb−Free)
Shipping
†
38 Units / Rail
1000 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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