DCDC Converter
15A Single-input Voltage, Synchronous
Buck Regulator with PMBus Interface
Digital SupIRBuck
IR38062
FEATURES
Internal LDO allows single 21V operation
Output Voltage Range: 0.5V to 0.875*PVin
0.5% accurate Reference Voltage
Programmable Switching Frequency
1.5MHz using Rt/Sync pin or PMBus
Internal Soft-Start with Pre-Bias Start-up
Enable input with Voltage Monitoring Capability
Remote Sense Amplifier with True Differential
Voltage Sensing
Fast mode I2C and 400 kHz PMBus interface
Sequencing and tracking capable
Selectable analog mode or digital mode
66 PMBus commands for configuration, control,
fault protection and telemetry.
Thermally compensated current
configurable overcurrent responses
Optional light load efficiency mode
External synchronization with Smooth Clocking
Dedicated output voltage sensing protection
which remains active even when Enable is low.
Integrated MOSFETs and Bootstrap diode
Operating junction temp: -40 C<Tj<125 C
Small Size 5mmx7mm PQFN
Pb-Free (RoHS Compliant)
o
o
DESCRIPTION
The IR38062 PMBus SupIRBuck™ is an easy-to-use,
fully integrated and highly efficient DC/DC regulator
with I2C/PMBus interface. The onboard PWM controller
and MOSFETs make IR38062 a space-efficient
solution, providing accurate power delivery for low
output voltage and high current applications.
The IR38062 can be comprehensively configured via
PMBus and the configuration stored in internal
memory. In addition, PMBus commands allow run-time
control, fault status and telemetry.
The IR38062 can also operate as a standard analog
regulator without any programming and can provide
current and temperature telemetry in an analog format.
up
to
limit
with
APPLICATIONS
Server Applications
Netcomm applications
Embedded telecom Systems
Distributed Point Of Load Architectures
ORDERING INFORMATION
Base Part Number
IR38062
Package Type
QFN 5 mm x 7 mm
Standard Pack
Form
Quantity
Tape and Reel
4000
Orderable Part Number
IR38062MTRPBF
1
Rev 3.14
Mar 14, 2018
IR38062
BASIC APPLICATION
5.5V <Vin<21V
P1V8 Track_EN
Vcc/
LDO_out
Vin
PVin
Boot
SW
Vsns
RS+
Vo
PGood
PGood
Rt/SYNC
RS-
SAlert/TMON
En/FCCM
SCL/OCSet
SDA/IMON
RSo
Fb
Comp
PGnd LGnd
Vp
ADDR
Figure 1: Typical Application Circuit
Figure 2: Performance Curve
PINOUT DIAGRAM
Note:
Pins 23 and 26 are connected internally
but appear separated externally (refer to
assembly drawing)
Figure 3: IR38062 package (Top View) 5mm x 7mm PQFN
2
Rev 3.14
Mar 14, 2018
IR38062
BLOCK DIAGRAM
Figure 4: IR38062 Simplified Block Diagram
3
Rev 3.14
Mar 14, 2018
IR38062
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
PVIN
2
Boot
3
¯¯¯¯¯¯¯¯¯ *
Track_En
Input voltage for power stage. Bypass capacitors between PVin and PGND should
be connected very close to this pin and PGND. Typical applications use 4 X22 uF
input capacitors and a low ESR, low ESL 0.1uF decoupling capacitor in a
0603/0402 case size. A 3.3nF capacitor may also be used in parallel with these
input capacitors to reduce ringing on the Sw node.
Supply voltage for high side driver. A 0.1uF capacitor should be connected from this
pin to the Sw pin. For PVin > 16V, it is recommended to use a 1 ohm to 4.02 ohm
resistor in series with the boot capacitor.
Pull low to enable tracking function. For normal, non-tracking operation, connect a
100 kOhm resistor from this pin to P1V8. An alternative to using 100kohm to P1V8
is to connect a 750 kohm resistor from Track_En# to LGND when the Track_En#
pin is not used for a tracking function. One of these two options must be used to
disable tracking functionality. The 100kOhm is the preferred method.
Used for sequencing and tracking applications. Leave open if not used.
Sense pin for OVP and PGood
Inverting input to the error amplifier. This pin is connected directly to the output of
the regulator or to the output of the remote sense amplifier, via resistor divider to
set the output voltage and provide feedback to the error amplifier.
Output of error amplifier. An external resistor and capacitor network is typically
connected from this pin to FB to provide loop compensation.
Remote Sense Amplifier Output
Remote Sense Amplifier input. Connect to ground at the load.
Remote Sense Amplifier input. Connect to output at the load.
Power Good status pin. Output is open drain. Connect a pull up resistor from this
pin to VCC. If the power good voltage before VCC UVLO needs to be limited to <
500 mV, use a 49.9K pullup, otherwise a 4.99K pullup will suffice.
Power ground. This pin should be connected to the system’s power ground plane.
Bypass capacitors between PVin and PGND should be connected very close to the
PVIN pin (pin 1) and this pin.
Signal ground for internal reference and control circuitry.
In analog mode, use an external resistor from this pin to GND to set the switching
frequency. The resistor should be placed very close to the pin. This pin can also be
used for external synchronization. In digital mode this pin is typically left floating
however a 15K resistor from this pin to GND may be used instead of floating the
pin.
Enable pin to turn on and off the IC. In analog mode, also serves as a mode pin,
forcing the converter to operate in CCM when pulled to<3.1V.
A resistor should be connected from this pin to LGnd to set the PMBus address
offset for the device. It is recommended to provide a placement for a 10 nF
capacitor in parallel with the offset resistor. If communication is not needed, as in
analog mode, this pin should be left floating.
4
5
6
7
8
9
10
11
Vp
Vsns
FB
COMP
RSo
RS-
RS+
PGood
12,25
13
PGND
LGND
14
RT/Sync
15
EN/FCCM
16
ADDR
4
Rev 3.14
Mar 14, 2018
IR38062
PIN #
PIN NAME
PIN DESCRIPTION
17
SALERT
¯¯¯¯¯¯¯
/TMON
SDA/IMON
18
19
SCL/OCSet
20
21
22
23,26
24
P1V8
Vin
VCC
NC
SW
SMBus ¯¯¯¯ line; open drain SMBALERT# pin. This should be pulled up to 3.3V-
Alert
5V with a 1K-5K resistor; this pin provides a voltage proportional to the junction
temperature if digital communication is not needed, as in analog mode.
SMBus data serial input/output line; This should be pulled up to 3.3V-5V with a 1K-
5K resistor; this pin provides a voltage proportional to the output current if digital
communication is not needed, as in analog mode.
SMBus clock line; This should be pulled up to 3.3V-5V with a 1K-5K resistor. This
pin is used to set OC thresholds if digital communication is not needed, as in analog
mode. In analog mode recommend 4.7KΩ for the pull-up to VCC or pull down to
GND when setting the OCP value.
This is the supply for the digital circuits; bypass with a minimum 2.2uF capacitor to
PGnd. A 10uF capacitor is recommended.
Input Voltage for LDO.
Bias Voltage for IC and driver section, output of LDO. Add 10 uF bypass cap from
this pin to PGnd.
NC
Switch node. This pin is connected to the output inductor.
*Design has simulated the Track_En# input threshold test for a 750K over:
the temperature range of -40 to 150degC,
Vcc of 4.5V to 5.5V
Over all corners of silicon
5
Rev 3.14
Mar 14, 2018
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