NJU7706/07
VOLTAGE DETECTOR
GENERAL DESCRIPTION
The NJU7706/07 is a high precision voltage detector with a
built-in delay time generator of fixed time.
The NJU7706/07 is useful for preventing malfunction of
microprocessor or DSP through monitoring power supply voltage.
The delay function achieves set wait time when supply voltage
is unstable. Moreover, the delay function can make a sequence
that other devices in application work and stabilize before
microcomputer or DSP works.
The detection voltage is internally fixed with an accuracy of 1.0%,
and three fixed delay times 50ms, 100ms and 200ms are
available. Manual reset function can output reset signal
irrespective of detection voltage.
NJU7706 is Nch. Open Drain and NJU7707 is a C-MOS output
type.
Small packaging makes NJU7706 and NJU7707 suitable for
space conscious applications.
PACKAGE OUTLINE
NJU7706/07F
FEATURES
High Precision Detection Voltage
±1.0%
Low Quiescent Current
1.3µA typ.
Detection Voltage Range
1.5
∼
6.0V(0.1V step)
Delay Time(Built-in Fixed Type)
50ms /100ms /200ms(Built-in Fixed Type)
ON/OFF switch of delay time(DSW pin)
Manual Reset
Active “L” : NJU770*F**A
Active "H" : NJU770*F**B
Output Configuration
NJU7706: Nch. Open Drain type
NJU7707: C-MOS Output type
Package Outline
SOT-23-5
PIN CONFIGURATION
5
4
1 2 3
NJU7706/07F
PIN FUNCTION
1.DSW
2.V
SS
3.MR
4.V
OUT
5.V
DD
Ver.2007-08-03
-1-
NJU7706/07
NJU7706
(Ta=25°C)
RATINGS
UNIT
+10
V
V
V
SS
-0.3
∼
+10
V
V
SS
-0.3∼V
DD
+0.3
V
V
SS
-0.3∼V
DD
+0.3
50
mA
350(*1)
Power Dissipation
P
D
SOT-23-5
mW
200(*2)
Operating Temperature
Topr
-40
∼
+85
°C
Storage Temperature
Tstg
-40
∼
+125
°C
(*1) : Mounted on glass epoxy board based on EIA/JEDEC. (114.3x76.2x1.6mm: 2Layers)
(*2) : Device itself
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
Detection Voltage
V
DET
Hysteresis Voltage
V
HYS
Quiescent Current
Output Current
I
SS
I
OUT
(Ta=25°C)
MAX. UNIT
+1.0%
V
130
mV
1.7
µA
2.2
−
mA
−
0.1
µA
−
57.5
115
230
300
V
DD
0.3
V
DD
0.3
V
DD
V
DD
-1.5
ppm/°C
ms
ms
ms
µs
V
V
V
V
V
V
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
Input Voltage
V
DD
Output Voltage
V
OUT
Input Voltage of DSW pin
V
DSW
Input Voltage of MR pin
V
MR
Output Current
I
OUT
TEST CONDITION
V
DD
=V
DET
+1V
Nch,V
DS
=0.5V
V
DET
=1.5V
∼
1.9V Version
V
DET
=2.0V
∼
6.0V Version
V
DD
=1.2V
V
DD
=2.4V (≥2.7V Version)
Output Leak Current
I
LEAK
V
DD
=V
OUT
=9V
Detection Voltage
Temperature
∆
V
DET
/∆Ta Ta=0
∼
+85°C
Coefficient
Delay Time 1
t
d1
V
DD
=V
DET
+1V,
DSW=”L Level”
NJU7706F***1
NJU7706F***2
NJU7706F***3
V
DD
=V
DET
+1V, DSW=”H Level”
MIN.
-1.0%
70
−
−
0.75
4.5
−
−
42.5
85
170
25
1.5
0
1.5
0
V
DD
-0.3
0
TYP.
−
90
1.0
1.3
2.0
7.0
−
±100
50
100
200
100
−
−
−
−
−
−
Delay Time 2
t
d2
V
DSW_H
Input Voltage of
DSW pin
V
DSW_L
V
MR_H
Input Voltage of
MR pin (Active “L”)
V
MR_L
V
MR_H
Input Voltage of
MR pin (Active “H”)
V
MR_L
Impedance of
1.0
2.0
3.0
R
MR
MΩ
MR pin
Operating Voltage
0.8
9
V
V
DD
R
L
=100kΩ
−
(*3)
(*3): The minimum operating voltage(V
OPL
) indicates the same value of the input voltage(V
DD
) on condition that V
OUT
becomes 10% or less of the input voltage(V
DD
).
-4-
Ver.2007-08-03
NJU7706/07
TEST CIRCUIT
Circuit Operating Current TEST CIRCUIT
Detection voltage / Minimum operating voltage
TEST CIRCUIT
A
V
DD
Iss
R
L
V
DD
V
OUT
V
OUT
V
DD
MR
V
DET
/
V
OPL
V
DD
DSW
NJU7706
V
DSW
NJU7706
MR
V
OUT
V
V
SS
V
SS
MR pin Input voltage TEST CIRCUIT
Leak current / Output current TEST CIRCUIT
R
L
V
DD
V
DD
V
OUT
V
OUT
DSW
V
SS
MR
V
DD
I
LEAK
/ I
OUT
V
OUT
A
V
DD
NJU7706
NJU7706
DSW
V
V
MR
V
MR
V
SS
MR
V
OUT
/ V
DS
V
Delay time1 TEST CIRCUIT
Oscilloscope
Delay time2 TEST CIRCUIT
Oscilloscope
R
L
V
DD
ch1 ch2
R
L
V
DD
ch1 ch2
NJU7706
V
DD
DSW
V
SS
V
OUT
V
DD
MR
DSW
NJU7706
V
SS
V
OUT
MR
Ver.2007-08-03
-5-
FPGA/CPLD
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