CM2030
HDMI Transmitter Port
Protection and Interface
Device
Product Description
The CM2030 HDMI Transmitter Port Protection and Interface
Device is specifically designed for next generation HDMI Host
interface protection.
An integrated package provides all ESD, level shifting/isolation,
overcurrent output protection and backdrive protection for an HDMI
port in a single 38−pin TSSOP package.
The CM2030 also incorporates a silicon overcurrent protection
device for +5 V supply voltage output to the connector.
CM2030 is ideal for applications which do not require HDMI
certification but can benefit from level shifters and backdrive
protection.
Features
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TSSOP 38
TR SUFFIX
CASE 948AG
•
•
•
•
•
•
•
•
•
Supports Thin Dielectric and 2−layer Boards
Minimizes TMDS Skew with 0.05 pF Matching
Long HDMI Cable Support with Integrated I
2
C Accelerator
Supports Direct Connection to CEC Microcontroller
Integrated I
2
C Level Shifting to CMOS Level Including Low
Logic Level Voltages
Integrated 8 kV ESD Protection and Backdrive Protection on All
External I/O Lines
Multiport I
2
C Support Eliminates Need for Analog Mux on DDC
Lines
Simplified Layout with Matched 0.5 mm Trace Spacing
These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAM
CM2030−A0TR
CM2030−A0TR = Specific Device Code
ORDERING INFORMATION
Device
CM2030−A0TR
Package
TSSOP−38
(Pb−Free)
Shipping
†
2500/Tape & Reel
Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
•
PC and Consumer Electronics
•
Set Top Box, DVD RW, PC, Graphics Cards
©
Semiconductor Components Industries, LLC, 2012
March, 2012
−
Rev. 8
1
Publication Order Number:
CM2030/D
CM2030
ELECTRICAL SCHEMATIC
5V_SUPPLY
TMDS_D2+
TMDS_GND
TMDS_D2−
TMDS_D1+
TMDS_GND
TMDS_D1−
TMDS_D0+
TMDS_GND
TMDS_D0−
TMDS_CK+
TMDS_GND
TMDS_CK−
5V SUPPLY
LV SUPPLY
CMOS/I
2
C
Level Shift
Dynamic
Pullup
DDC_CLK_OUT
DDC_DAT_IN
LV SUPPLY
CMOS/I
2
C
Level Shift
5V SUPPLY
Dynamic
Pullup
DDC_DAT_OUT
CE_SUPPLY
DDC_CLK_IN
LV SUPPLY
I
S
HOTPLUG_DET_IN
3I
S
CE_SUPPLY
HOTPLUG_DET_OUT
CE_REMOTE_IN
Active Slew
Rate Limiting
CE_REMOTE_OUT
5V_SUPPLY
55 mA
Overcurrent
Switch
5V_OUT
PACKAGE / PINOUT DIAGRAM
Top View
5V_SUPPLY
LV_SUPPLY
GND
TMDS_D2+
TMDS_GND
TMDS_D2−
TMDS_D1+
TMDS_GND
TMDS_D1−
TMDS_D0+
TMDS_GND
TMDS_D0−
TMDS_CK+
TMDS_GND
TMDS_CK−
CE_REMOTE_IN
DDC_CLK_IN
DDC_DAT_IN
HOTPLUG_DET_IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
5V_OUT
CE_SUPPLY
GND
TMDS_D2+
TMDS_GND
TMDS_D2−
TMDS_D1+
TMDS_GND
TMDS_D1−
TMDS_D0+
TMDS_GND
TMDS_D0−
TMDS_CK+
TMDS_GND
TMDS_CK−
CE_REMOTE_OUT
DDC_CLK_OUT
DDC_DAT_OUT
HOTPLUG_DET_OUT
38−Pin TSSOP Package
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2
CM2030
Table 1. PIN DESCRIPTIONS
Pins
4, 35
6, 33
7, 32
9, 30
10, 29
12, 27
13, 26
15, 24
16
23
17
22
18
21
19
20
2
37
1
38
3, 5, 8, 11,
14, 25, 28,
31, 34, 36
Name
TMDS_D2+
TMDS_D2−
TMDS_D1+
TMDS_D1−
TMDS_D0+
TMDS_D0−
TMDS_CK+
TMDS_CK−
CE_REMOTE_IN
CE_REMOTE_OUT
DDC_CLK_IN
DDC_CLK_OUT
DDC_DAT_IN
DDC_DAT_OUT
HOTPLUG_DET_IN
HOTPLUG_DET_OUT
LV_SUPPLY
CE_SUPPLY
5V_SUPPLY
5V_OUT
GND / TMDS_GND
ESD Level
8 kV (Note 3)
8 kV (Note 3)
8 kV (Note 3)
8 kV (Note 3)
8 kV (Note 3)
8 kV (Note 3)
8 kV (Note 3)
8 kV (Note 3)
2 kV (Note 4)
8 kV(Note 3)
2 kV (Note 4)
8 kV (Note 3)
2 kV (Note 4)
8 kV (Note 3)
2 kV (Note 4)
8 kV (Note 3)
2 kV (Note 4)
2 kV
(Notes 2 & 4)
2 kV (Note 4)
8 kV (Note 3)
N/A
Description
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
TMDS 0.9 pF ESD Protection (Note 1)
CE_SUPPLY Referenced Logic Level In
5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6)
LV_SUPPLY Referenced Logic Level In
5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6)
LV_SUPPLY Referenced Logic Level In
5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD (Note 6)
LV_SUPPLY Referenced Logic Level In
5V_SUPPLY Referenced Logic Level Out plus 10 pF ESD. A 0.1
mF
Bypass
Ceramic Capacitor is Recommended on this Pin (Note 2).
Bias for CE / DDC / HOTPLUG Level Shifters
CEC Bias Voltage. Previously CM2020 ESD_BYP Pin.
Current Source for 5V_OUT, VREF for DDC I
2
C Voltage References, and Bias for
8 kV ESD Pins.
55 mA Minimum Overcurrent Protected 5 V Output. This Output Must be
Bypassed with a 0.1
mF
Ceramic Capacitor.
GND Reference
1. These 2 pins need to be connected together in−line on the PCB. See recommended layout diagram.
2. This output can be connected to an external 0.1
mF
ceramic capacitor/pads to maintain backward compatibility with the CM2020.
3. Standard IEC 61000−4−2, C
DISCHARGE
= 150 pF, R
DISCHARGE
= 330
W,
5V_SUPPLY and LV_SUPPLY within recommended operating
conditions, GND = 0 V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1
mF
ceramic capacitor connected
to GND.
4. Human Body Model per MIL−STD−883, Method 3015, C
DISCHARGE
= 100 pF, R
DISCHARGE
= 1.5 kW, 5V_SUPPLY and LV_SUPPLY within
recommended operating conditions, GND = 0 V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1
mF
ceramic
capacitor connected to GND.
5. These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector.
6. The slew−rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins.
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CM2030
BACKDRIVE PROTECTION AND ISOLATION
Backdrive current is defined as the undesirable current
flow through an I/O pin when that I/O pin’s voltage exceeds
the related local supply voltage for that circuitry. This is
a potentially common occurrence in multimedia
entertainment systems with multiple components and
several power plane domains in each system.
For example, if a DVD player is switched off and an
HDMI connected TV is powered on, there is a possibility of
reverse current flow back into the main power supply rail of
the DVD player from pull−ups in the TV. As little as a few
milliamps of backdrive current flowing back into the power
rail can charge the DVD player’s bulk bypass capacitance on
the power rail to some intermediate level. If this level rises
above the power−on−reset (POR) voltage level of some of
the integrated circuits in the DVD player, then these devices
may not reset properly when the DVD player is turned back
on.
If any SOC devices are incorporated in the design which
have built−in level shifter and/or ESD protection structures,
there can be a risk of permanent damage due to backdrive.
In this case, backdrive current can forward bias the on−chip
ESD protection structure. If the current flow is high enough,
even as little as a few milliamps, it could destroy one of the
SOC chip’s internal DRC diodes, as they are not designed for
passing DC.
To avoid either of these situations, the CM2030 was
designed to block backdrive current, guaranteeing less than
5
mA
into any I/O pin when the I/O pin voltage exceeds its
related operating CM2030 supply voltage.
Figure 1. Backdrive Protection Diagram.
DISPLAY DATA CHANNEL (DDC) LINES
The DDC interface is based on the I
2
C serial bus protocol
for EDID configuration.
Dynamic Pullups
Based on the HDMI specification, the maximum
capacitance of the DDC line can approach 800 pF (50 pF
from source, 50 pF from sink, and 700 pF from cable). At
the upper range of capacitance values (i.e. long cables), it
becomes impossible for the DDC lines to meet the I
2
C
timing specifications with the minimum pull−up resistor of
1.5 kΩ.
For this reason, the CM2030 was designed with an
internal I
2
C accelerator to meet the AC timing specification
even with very long and non−compliant cables.
The internal accelerator increases the positive slew rate of
the DDC_CLK_OUT and DDC_DAT_OUT lines whenever
the sensed voltage level exceeds 0.3*5V_SUPPLY
(approximately 1.5 V). This provides faster overall risetime
in heavily loaded situations without overloading the
multi−drop open drain I
2
C outputs elsewhere.
Figure 2 demonstrates the “worst case” operation of the
dynamic CM2030 DDC level shifting circuitry (bottom)
against a discrete NFET common−gate level shifter circuit
with a typical 1.5 kW pullup at the source (top.) Both are
shown driving an off−spec, but unfortunately readily
available 31 m HDMI cable which exceeds the 700 pF
HDMI specification. Some widely available HDMI cables
have been measured at
over 4 nF.
When the standard I/OD cell releases the NFET discrete
shifter, the risetime is limited by the pullup and the parasitics
of the cable, source and sink. For long cables, this can extend
the risetime and reduce the margin for reading a valid “high”
level on the data line. In this case, an HDMI source may not
be able to read uncorrupted data and will not be able to
initiate a link.
With the CM2030’s dynamic pullups, when the ASIC
driver releases its DDC line and the “OUT” line reaches at
least 0.3*VDD (of 5V_SUPPLY), then the “OUT” active
pullups are enabled and the CM2030 takes over driving the
cable until the “OUT” voltage approaches the 5V_SUPPLY
rail.
The internal pass element and the dynamic pullups also
work together to damp reflections on the longer cables and
keep them from glitching the local ASIC.
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CM2030
Figure 2. Dynamic DDC Pullups
(Discrete
−
Top, CM2030
−
Bottom; 3.3 V ASIC
−
Left, 5 V Cable
−
Right)
I
2
C Low Level Shifting
In addition to the Dynamic Pullups described in the
previous section, the CM2030 also incorporates improved
I
2
C low−level shifting on the DDC_CLK_IN and
DDC_DAT_IN lines for enhanced compatibility.
Typical discrete NFET level shifters can advertise
specifications for low R
DS
[on], but usually state relatively
high V
[GS]
test parameters, requiring a ‘switch’ signal (gate
voltage) as high as 10 V or more. At a sink current of 4 mA
for the ASIC on DDC_XX_IN, the CM2030 guarantees no
more than 140 mV increase to DDC_XX_OUT, even with
a switching control of 2.5 V on LV_SUPPLY.
When I
2
C devices are driving the external cable, an
internal pulldown on DDC_XX_IN guarantees that the VOL
seen by the ASIC on DDC_XX_IN is equal to or lower than
DDC_XX_OUT.
Multiport DDC Multiplexing
By switching LV_SUPPLY, the DDC/HPD blocks can be
independently disabled by engaging their inherent
“backdrive” protection. This allows N:1 multiplexing of the
low−speed HDMI signals without any additional FET
switches.
CONSUMER ELECTRONICS CONTROL (CEC)
The Consumer Electronics Control (CEC) line is a high
level command and control protocol, based on a single wire
multidrop open drain communication bus running at
approximately 1 kHz (See Figure 3). While the HDMI link
provides only a single point−to−point connection, up to ten
(10) CEC devices may reside on the bus, and they may be
daisy chained out through other physical connectors
including other HDMI ports or other dedicated CEC links.
The high level protocol of CEC can be implemented in
a simple microcontroller or other interface with any I/OD
(input/open−drain) GPIO.
RX
TX
CEC
I/OD
GPIO
To limit possible EMI and ringing in this potentially
complex connection topology, the rise− and fall−time of this
line are limited by the specification. However, meeting the
slew−rate limiting requirements with additional discrete
circuitry in this bi−directional block is not trivial without an
additional RX/TX control line to limit the output slew−rate
without affecting the input sensing (See Figure 4).
RX
TX
TX_EN
CEC
Slew Rate
Limited
3−State Buffer
Figure 4. Three−Pin External Buffer Control
Figure 3. Typical
mC
I/OD Driver
Simple CMOS buffers cannot be used in this application
since the load can vary so much (total pullup of 27 kW to less
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