HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
◆
IDT7130SA/LA
IDT7140SA/LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
—
Active: 550mW (typ.)
—
Standby: 5mW (typ.)
– IDT7130/IDT7140LA
—
Active: 550mW (typ.)
—
Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
On-chip port arbitration logic (IDT7130 Only)
BUSY
output flag on IDT7130;
BUSY
input on IDT7140
INT
flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
9L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
10
,
(1,2)
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2689 drw 01
(2)
NOTES:
1. IDT7130 (MASTER):
BUSY
is open drain output and requires pullup resistor.
IDT7140 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor.
FEBRUARY 2018
1
DSC-2689/18
©2018 Integrated Device Technology, Inc.
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-
more-bit memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate con-
trol, address, and I/O pins that permit independent asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by
CE,
permits the on chip circuitry
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 550mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze
or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP
and STQFP. Military grade products are manufactured in compli-
ance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.
Pin Configurations
(1,2,3)
A
0R
A
1R
A
2R
A
3R
OE
R
INT
R
BUSY
R
R/W
R
CE
R
V
CC
CE
L
R/W
L
BUSY
L
INT
L
OE
L
A
0L
42 41 40 39 38 37 36 35 34 33 32 31
43
30
44
29
45
28
46
27
26
47
25
48
7130/40
(4)
F48
24
1
23
2
22
3
4
21
20
5
19
6
7 8 9 10 11 12 13 14 15 16 17 18
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
GND
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
2689 drw 03F
I/O
2L
I/O
1L
I/O
0L
A
9L
A
8L
A
7L
A
6L
INDEX
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. L48 package body is approximately .57 in x .57 in x .68 in.
F48 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
18 17 16 15 14 13 12 11 10 9 8 7
6
19
20
5
4
21
22
3
23
2
1
24
7130/40
(4)
L48
48
25
26
47
46
27
28
45
44
29
43
30
31 32 33 34 35 36 37 38 39 40 41 42
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
OE
L
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
OE
R
I/O
7R
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
2
I/O
6R
2689 drw 03L
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
CE
L
R/W
L
BUSY
L
INT
L
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
IDT7130/40
41
P or C
40
9
P48
(4,5)
10
39
&
11
C48
(4,5)
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
V
CC
CE
R
R/W
R
BUSY
R
INT
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
2689 drw 02
,
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. P48 package body is approximately .55 in x .61 in x .19 in.
C48 package body is approximately .62 in x 2.43 in x .15 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
20 19 18 17 16 15 14 13 12 11 10 9 8
7
21
22
6
5
23
4
24
3
25
26
2
7130/40
(4)
J52
1
27
52
28
51
29
50
30
49
31
48
32
47
33
34 35 36 37 38 39 40 41 42 43 44 45 46
I/O
3L
I/O
2L
I/O
1L
I/O
0L
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
OE
L
N/C
INT
L
BUSY
L
R/W
L
CE
L
V
CC
CE
R
R/W
R
BUSY
R
INT
R
N/C
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
I/O
7R
N/C
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
4
A
1R
A
0R
OE
R
2689 drw 04
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
N/C
N/C
N/C
INT
R
BUSY
R
R/W
R
CE
R
V
CC
V
CC
CE
L
R/W
L
BUSY
L
INT
L
N/C
N/C
N/C
48 47 46 4544 43 42 4140 39 383736 35 34 33
49
32
50
31
51
30
52
29
28
53
54
27
55
26
7130/40
25
56
PP64 & PN64
(4)
57
24
58
23
59
22
21
60
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 1213 14 1516
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
I/O
5R
I/O
4R
N/C
I/O
3R
I/O
2R
I/O
1R
I/O
0R
GND
GND
N/C
I/O
7L
I/O
6L
I/O
5L
I/O
4L
N/C
I/O
3L
2689 drw 05
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PP64 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
