2:2, Differential-to-LVPECL/LVDS
Clock Multiplexer
General Description
The ICS859S0212I is a 2:2 Differential-to-LVPECL/ LVDS Clock
Multiplexer which can operate up to 3GHz. The ICS859S0212I has 2
selectable differential PCLKx, nPCLKx clock inputs. The PCLKx,
nPCLKx input pairs can accept LVPECL, LVDS or CML levels. The
fully differential architecture and low propagation delay make it ideal
for use in clock distribution circuits.
ICS859S0212I
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
•
•
High speed 2:1 differential multiplexer with a 1:2 fanout buffer
Two differential LVPECL or LVDS output pairs
Two selectable differential PCLKx, nPCLKx input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
Part-to-part skew: 100ps (maximum)
Propagation delay: 565ps (typical) at 3.3V
Additive phase jitter, RMS: 0.21ps (typical) at 3.3V
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OE
Pullup
CLK_SEL
Pulldown
Pin Assignment
CLK_SEL
PCLK0
nPCLK0
PCLK1
nPCLK1
nc
OE
SEL_OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
EE
Q0
nQ0
Q1
nQ1
V
EE
V
CC_TAP
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
0
Q0
nQ0
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
Q1
1
nQ1
ICS859S0212I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
SEL_OUT
Pullup
ICS859S0212BGI REVISION A JUNE 4, 2012
1
©2012 Integrated Device Technology, Inc.
ICS859S0212I Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10, 15
11, 12
13, 14
16
Name
CLK_SEL
PCLK0
nPCLK0
PCLK1
nPCLK1
nc
OE
SEL_OUT
V
CC_TAP
V
EE
nQ1, Q1
nQ0, Q0
V
CC
Input
Input
Input
Input
Input
Unused
Input
Input
Power
Power
Output
Output
Power
Pullup
Pullup
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
No connect.
Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels.
Output select pin. When LOW, selects LVDS levels. When HIGH, selects LVPECL
levels. LVCMOS/LVTTL interface levels. See Table 3B.
Positive supply pin. See Table 3A.
Negative supply pins.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Positive supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
VCC/2
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
75
Maximum
Units
pF
k
k
k
ICS859S0212BGI REVISION A JUNE 4, 2012
2
©2012 Integrated Device Technology, Inc.
ICS859S0212I Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Function Tables
Table 3A. V
CC_TAP
Function Table
Outputs
Q[0:1], nQ[0:1]
LVPECL
LVPECL
LVDS
LVDS
Output Level Supply
2.5V
3.3V
2.5V
3.3V
V
CC_TAP
V
CC
V
CC
V
CC
Float
Table 3B. SEL_OUT Function Table
Input
SEL_OUT
1 (default)
0
Outputs
Q[0:1], nQ[0:1]
LVPECL
LVDS
Table 4A. Clock Input Function Table
Inputs
CLK_SEL
0 (default)
1
Outputs
Q[0:1], nQ[0:1]
PCLK0, nPCLK0
PCLK, nPCLK1
Table 4B. Output Enable Function Table
Inputs
OE
0
1 (default)
Outputs
Q[0:1], nQ[0:1]
Low, High
Normal Operation
ICS859S0212BGI REVISION A JUNE 4, 2012
3
©2012 Integrated Device Technology, Inc.
ICS859S0212I Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
10mA
15mA
92C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
I
CC_TAP
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
55
5
Units
V
V
mA
mA
Table 5B. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
I
CC_TAP
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
50
5
Units
V
V
mA
mA
Table 5C. LVDS Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
CC
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
80
Units
V
mA
Table 5D. LVDS Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
CC
I
CC_TAP
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Power Supply Current
4
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
76
5
Units
V
V
mA
mA
ICS859S0212BGI REVISION A JUNE 4, 2012
©2012 Integrated Device Technology, Inc.
ICS859S0212I Data Sheet
2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 5E. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= 3.465V
V
CC
= 2.625V
CLK_SEL
I
IH
Input High Current
OE,
SEL_OUT
CLK_SEL
I
IL
Input Low Current
OE,
SEL_OUT
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
10
Units
V
V
V
V
µA
µA
µA
µA
Input Low Voltage
Table 5F. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
Input Low Current
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
PCLK0, PCLK1,
nPCLK0, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-10
-150
0.15
1.2
V
CC
– 1.4
V
CC
– 2.0
0.6
1.3
V
CC
V
CC
– 0.9
V
CC
– 1.7
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: Outputs terminated with 50
to V
CC
– 2V.
Table 5G. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
Input Low Current
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE2
Peak-to-Peak Output Voltage Swing
PCLK0, PCLK1,
nPCLK0, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
-10
-150
0.15
1.2
V
CC
– 1.4
V
CC
– 2.0
0.4
1.3
V
CC
V
CC
– 0.9
V
CC
– 1.5
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
ICS859S0212BGI REVISION A JUNE 4, 2012
5
©2012 Integrated Device Technology, Inc.
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
