For NPN test circuit reverse diode and voltage polarities.
Figure 1. Power Derating
Figure 2. Switching Times Test Circuit
ELECTRICAL CHARACTERISTICS
(T
C
= 25_C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 1)
(I
C
= 0.1 Adc, I
B
= 0)
Collector Cutoff Current
(V
CE
= 125, I
B
= 0)
Collector Cutoff Current
(V
CE
= Rated V
CB
, V
BE(off)
= 1.5 Vdc)
(V
CE
= Rated V
CB
, V
BE(off)
= 1.5 Vdc, T
J
= 150_C)
Emitter Cutoff Current (V
BE
= 5.0 Vdc, I
C
= 0)
ON CHARACTERISTICS
(Note 1)
DC Current Gain
(I
C
= 10 Adc, V
CE
= 5.0 Vdc)
(I
C
= 15 Adc, V
CE
= 5.0 Vdc)
Collector−Emitter Saturation Voltage
(I
C
= 10 Adc, I
B
= 100 mA)
(I
C
= 15 Adc, I
B
= 150 mA)
Base−Emitter On Voltage
I
C
= 10 A, V
CE
= 5.0 Vdc)
Base−Emitter Saturation Voltage
(I
C
= 15 Adc, I
B
= 150 mA)
DYNAMIC CHARACTERISTICS
Current−Gain Bandwidth Product
(I
C
= 10 Adc, V
CE
= 3.0 Vdc, f = 1.0 MHz)
Output Capacitance (V
CB
= 10 Vdc, I
E
= 0, f = 0.1 MHz)
MJ11022
MJ11021
[h
fe
]
C
ob
3.0
−
Mhz
pF
h
FE
400
100
−
−
−
−
15,000
−
2.0
3.4
2.8
3.8
−
MJ11021, MJ11022
MJ11021, MJ11022
V
CEO(sus)
I
CEO
I
CEV
250
−
−
−
−
−
1.0
0.5
5.0
2.0
Vdc
mAdc
mAdc
Symbol
Min
Max
Unit
I
EBO
mAdc
V
CE(sat)
Vdc
V
BE(on)
V
BE(sat)
Vdc
Vdc
−
−
75
400
600
−
Small−Signal Current Gain
(I
C
= 10 Adc, V
CE
= 3.0 Vdc, f = 1.0 kHz)
SWITCHING CHARACTERISTICS
Characteristic
Delay Time
Rise Time
Storage Time
Fall Time
1. Pulsed Test: Pulse Width = 300
ms,
Duty Cycle
v
2%.
(V
CC
= 100 V, I
C
= 10 A, I
B
= 100 mA
V
BE(off)
= 50 V) (See Figure 2)
h
fe
−
Symbol
t
d
t
r
t
s
t
f
Typical
NPN
PNP
150
1.2
4.4
10.0
75
0.5
2.7
2.5
Unit
ns
ms
ms
ms
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2
MJ11021(PNP)
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
1.0
0.7
0.5
0.3
0.2
0.1
0.1
0.07
0.05
0.03
0.02
0.01
0.01
SINGLE PULSE
0.05
0.02
0.01
MJ11022 (NPN)
D = 0.5
0.2
P
(pk)
R
qJC
(t) = r(t) R
qJC
R
qJC
(t) = 0.86°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
R
qJC
(t)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
50
100
200 300
500
1000
0.02
0.03 0.05
1.0
0.2
0.3 0.5
1.0
2.0
3.0 5.0
t, TIME (ms)
10
20
30
Figure 3. Thermal Response
30
IC, COLLECTOR CURRENT (AMPS)
5.0 ms
30
20
10
5.0
3.0
2.0
1.0
0.5
0.3
0.2
0
3.0
dc
T
J
= 175°C
SECOND BREAKDOWN LIMIT
BONDING WIRE LIMIT
THERMAL LIMITATION @ T
C
= 25°C
SINGLE PULSE
1.0 ms
0.1 ms
IC, COLLECTOR CURRENT (AMPS)
0.5 ms
L = 200
mH
I
C
/I
B1
≥
50
T
C
= 25°C
V
BE(off)
0 - 5.0 V
R
BE
= 47
W
DUTY CYLE = 10%
20
10
5.0 7.0
10
20
30 50
70
100 150 200
0
0 20
60
100
140
180
220
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
260
V
CE
, COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 4. Maximum Rated Forward Bias Safe
Operating Area (FBSOA)
FORWARD BIAS
Figure 5. Maximum RBSOA, Reverse Bias Safe
Operating Area
REVERSE BIAS
There are two limitations on the power handling ability of
a transistor average junction temperature and second
breakdown. Safe operating area curves indicate I
C
−
V
CE
limits of the transistor that must be observed for reliable
operation, i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 4 is based on T
J(pk)
= 175_C, T
C
is
variable dependIng on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
v
175_C. T
J(pk)
may be calculated from the data in
Figure 3. At high case temperatures thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
For inductive loads, high voltage and high current must be
sustained simultaneously during turn−off, in most cases,
with the base to emitter junction reverse biased. Under these
conditions the collector voltage must be hold to a safe level
at or below a specific value of collector current. This can be
accomplished by several means such as active clamping, RC
snubbing, load line shaping, etc. The safe level for these
devices is specified as Reverse Bias Safe Operating Area
and represents the voltage−current conditions during
reverse biased turn−off. This rating is verified under
clamped conditions so that the device is never subjected to
an avalanche mode. Figure 5 gives ROSOA characteristics.
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3
MJ11021(PNP)
PNP
10,000
7000
5000
hFE, DC CURRENT GAIN
3000
2000
T
J
= 25°C
1000
700
500
300
200
100
0.2
V
CE
= 5.0 Vdc
T
J
= 150°C
hFE, DC CURRENT GAIN
MJ11022 (NPN)
NPN
30,000
20,000
10,000
7000
5000
3000
2000
1000
700
500
T
J
= 25°C
T
J
= 150°C
V
CE
= 5.0 Vdc
T
J
= - 55°C
T
J
= - 55°C
0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0
I
C
, COLLECTOR CURRENT (A)
10
15 20
300
0.2 0.3
0.5 0.7 1.0
2.0 3.0
5.0 7.0
I
C
, COLLECTOR CURRENT (A)
10
15 20
Figure 6. DC Current Gain
PNP
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
I
C
= 15 A
3.5
I
C
= 10 A
3.0
I
C
= 5.0 A
2.5
2.0
1.5
1.0
0.5
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
I
B
, BASE CURRENT (mA)
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
4.0
T
J
= 25°C
4.0
I
C
= 15 A
3.5
I
C
= 10 A
3.0
I
C
= 5.0 A
2.5
2.0
1.5
1.0
0.5
0.5 0.7 1.0
2.0 3.0 5.0 7.0 10 20 30 50 70 100 200 300 500
I
B
, BASE CURRENT (mA)
T
J
= 25°C
NPN
Figure 7. Collector Saturation Region
PNP
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.1
V
BE(sat)
@ I
C
/I
B
= 100
V
BE
@ V
CE
= 5.0 V
V
CE(sat)
@ I
C
/I
B
= 100
0.2 0.3 0.5 0.7 1.0
2.0 3.0 5.0 7.0 10
20 30
50
70
T
J
= 25°C
VOLTAGE (VOLTS)
4.0
3.5
T
J
= 25°C
VOLTAGE (VOLTS)
3.0
2.5
2.0
1.5
1.0
0.5
0.1
V
BE(sat)
@ I
C
/I
B
= 100
V
BE
@ V
CE
= 5.0 V
0.2 0.3 0.5 0.7 1.0
NPN
V
CE(sat)
@ I
C
/I
B
= 100
2.0 3.0 5.0 7.0 10
20 30
50
COLLECTOR CURRENT (AMPS)
COLLECTOR CURRENT (AMPS)
Figure 8. “On” Voltages
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4
MJ11021(PNP)
MJ11022 (NPN)
PACKAGE DIMENSIONS
TO−204 (TO−3)
CASE 1−07
ISSUE Z
A
N
C
E
D
2 PL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. ALL RULES AND NOTES ASSOCIATED WITH
REFERENCED TO-204AA OUTLINE SHALL APPLY.
INCHES
MIN
MAX
1.550 REF
---
1.050
0.250
0.335
0.038
0.043
0.055
0.070
0.430 BSC
0.215 BSC
0.440
0.480
0.665 BSC
---
0.830
0.151
0.165
1.187 BSC
0.131
0.188
MILLIMETERS
MIN
MAX
39.37 REF
---
26.67
6.35
8.51
0.97
1.09
1.40
1.77
10.92 BSC
5.46 BSC
11.18
12.19
16.89 BSC
---
21.08
3.84
4.19
30.15 BSC
3.33
4.77
−T−
K
M
SEATING
PLANE
0.13 (0.005)
U
2
T Q
M
Y
M
V
H
L
G
−Y−
B
1
−Q−
0.13 (0.005)
DIM
A
B
C
D
E
G
H
K
L
N
Q
U
V
M
T Y
M
STYLE 1:
PIN 1. BASE
2. EMITTER
CASE: COLLECTOR
ON Semiconductor
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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