AS4C32M16SA
512Mbit Single-Data-Rate (SDR) SDRAM
AS4C32M16SA-7TCN & AS4C32M16SA-7TIN
AS4C32M16SA-7 CN & AS4C32M16SA-7 IN
32Mx16 (8M x 16 x 4 Banks)
4
Mar
6
AS4C32M16SA
REVISION HISTORY
Rev. 1.0 March 2012
Rev. 1.1 April 2012
Rev. 2.0 February 2014
initial version
Revised Operating-; Standby- and Refresh Currents
Die Shrink – A revision
Rev.
4.0
March
2016
Correcting errors:
Page 3 transfer rates up to 166 MHz ===> transfer rates up to 143MHz
Page 4 data transfer rates up to 166 MHz =====> data transfer rates up to 143 MHz
data rate of up to 166 MHz=========>data rate of upto 143 MHz
Page 5
- pin labelling errors
I/O1 ==> DQ0
I/O16 ==> DQ15
Page 6
= pin labelling errors
VDD===> VCC
VDDQ===> VCCQ
4
Mar
6
AS4C32M16SA
Overview
This section gives an overview of the 512M SDRAM product and describes its main characteristics.
Features
4 banks x 8Mbit x 16 organization
High speed data transfer rates up to 143 MHz
Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page for Sequential Type 1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Pre-charge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54 Pin TSOP II
Available in 54
II
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
ROHS Compliant*
4
Mar
6
AS4C32M16SA
Table 1 - Performance Table
-7
Description
The AS4C32M16SA is a four bank Synchronous DRAM organized as 4 banks x 8Mbit x 16. The
AS4C32M16SA achieves high speed data transfer rates up to 143 MHz by employing a chip
architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-leaved fashion allows random access operation to
occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up
to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
AS4C32M16SA-7TCN
AS4C32M16SA-7TIN
AS4C32M16SA-7BCN
AS4C32M16SA-7BIN
Org
32M x 16
32M x 16
32M x 16
32M x 16
Temperature
Commercial
0¡C to 70¡C
Industrial
-40¡C
to 85¡C
Commercial
0¡C to 70¡C
Industrial
-40¡C
to 85¡C
Max Clock (MHz)
143
143
143
143
Package
54pin TSOP II
54pin TSOP II
54 Ball FBGA
54 Ball FBGA
4
Mar
6
AS4C32M16SA
CLK
CKE
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
Data Input/Output
Data Mask
Power (+3.0V~3.3V)
Ground
Power for I/O’s (+3.0V~3.3V)
Ground for I/O’s
Not connected
V
CC
DQ0
V
CCQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
CCQ
DQ5
DQ6
V
SSQ
DQ7
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
356164V-01
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
CCQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
CCQ
DQ8
V
SS
CS
RAS
CAS
WE
A
0
–A
12
BA0, BA1
DQ0–DQ15
LDQM, UDQM
V
CC
V
SS
V
CCQ
V
SSQ
NC
NC
UDQM
CLK
CKE
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
4
Mar
6
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
