MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
Features
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•
•
•
•
•
•
•
Buffered Data Inputs
Common Clock
Clock Polarity Control
Q and Q Outputs
Double Diode Input Protection
Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Q3
Q0
Q0
D0
CLOCK
POLARITY
D1
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q3
D3
D2
Q2
Q2
Q1
Q1
MARKING DIAGRAM
16
14042BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
Publication Order Number:
MC14042B/D
MC14042B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
−55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs all
buffers switching)
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
1.0
2.0
4.0
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.002
0.004
0.006
−
−
−
−
−
−
−
±0.1
7.5
1.0
2.0
4.0
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
30
60
120
mAdc
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“0” Level
V
OH
Vdc
V
IL
Vdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (1.0
mA/kHz)
f + I
DD
I
T
= (2.0
mA/kHz)
f + I
DD
I
T
= (3.0
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
− 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
− V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
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MC14042B
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Propagation Delay Time, D to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 57 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 35 ns
Propagation Delay Time, Clock to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 135 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 57 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 35 ns
Clock Pulse Width
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Clock Pulse Rise and Fall Time
t
TLH
,
t
THL
5.0
10
15
5.0
10
15
Setup Time
t
su
5.0
10
15
50
30
25
0
0
0
−
−
−
Min
−
−
−
−
−
−
−
−
−
300
100
80
−
−
−
100
50
40
Typ
(Note 6)
100
50
40
220
90
60
220
90
60
150
50
40
−
−
−
50
25
20
Max
200
100
80
no
440
180
120
ns
440
180
120
ns
−
−
−
ms
15
5.0
4.0
ns
−
−
−
ns
Unit
ns
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
WH
Hold Time
t
h
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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