1.8V LVPECL Clock Divider
8P73S674
DATA SHEET
General Description
The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer.
The device has been designed for clock signal division and fanout in
wireless base station (radio and base band), high-end computing and
telecommunication equipment. The device is optimized to deliver
excellent phase noise performance. The 8P73S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew 1.8V LVPECL outputs are available for and support clock
output frequencies up to 1GHz (÷1 frequency division). 1.8V LVPECL
outputs are terminated 50 to GND. Outputs can be disabled to save
power consumption if not used. The device is packaged in a lead-free
(RoHS 6) 20-lead VFQFN package. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
•
•
•
•
•
•
•
•
•
•
•
Clock signal division and distribution
SiGe technology for high-frequency and fast signal rise/fall times
Four low-skew LVPECL clock outputs
Supports frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum Output frequency: 1GHz
Output skew: 100ps (maximum)
LVPECL output rise/fall time (20% - 80%): 220ps (maximum)
1.8V core and output supply mode
Supports 1.8V I/O LVCMOS logic levels for all control pins
-40°C to +85°C ambient operating temperature
Lead-free (RoHS 6) 20-lead VFQFN packaging
Block Diagram
IN
nIN
2x 50
Pin Assignment
nOEA
GND
÷N
Q0
nQ0
nIN
1
2
3
4
5
20
19
18
17
16
15
14
VCC
nQ1
Q1
nQ2
Q2
VCC
13
12
11
10
nQ0
8
VT
N[1:0]
nOEA
nOEB
Q1
nQ1
NC
VT
IN
Q2
nQ2
8P73S674
Q3
nQ3
N0
6
7
9
N1
nQ3
Q0
GND
20-pin, 2.15mm x 2.15mm, EPad, VFQFN Package
8P73S674 REVISION 1 12/17/14
1
nOEB
©2014 Integrated Device Technology, Inc.
Q3
8P73S674 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
EPAD
Name
nIN
NC
VT
IN
N0
GND
N1
nOEB
nQ3
Q3
V
CC
Q2
nQ2
Q1
nQ1
V
CC
Q0
nQ0
nOEA
GND
GND_EP
Input
Unused
—
Input
Input
Power
Input
Input
Output
Output
Power
Output
Output
Output
Output
Power
Output
Output
Input
Power
Power
Type
—
—
—
—
Pulldown
—
Pulldown
Pulldown
—
—
—
—
—
—
—
—
—
—
Pulldown
—
—
Description
Clock signal inverting differential input. Internal termination 50 to VT.
Not connected.
Leave open if IN, nIN is used with LVDS signals.
Clock signal non-inverting differential input. Internal termination 50 to VT.
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
Power supply ground.
Frequency divider control. 1.8V LVCMOS/LVTTL interface levels.
Output enable control for the Q1, Q2 and Q3 outputs.
1.8V LVCMOS/LVTTL interface levels.
Differential clock output 3. 1.8V LVPECL output levels.
Supply voltage for the clock outputs.
Differential clock output 2. 1.8V LVPECL output levels.
Differential clock output 1. 1.8V LVPECL output levels.
Supply voltage for the clock outputs.
Differential clock output 0. 1.8V LVPECL output levels.
Output enable control for the Q0 output.
1.8V LVCMOS/LVTTL interface levels.
Power supply ground.
Exposed package pad negative supply voltage (GND).
Return current path for the Q0, Q1, Q2 and Q3 outputs.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
1.8V LVPECL CLOCK DIVIDER
2
REVISION 1 12/17/14
8P73S674 DATA SHEET
Truth Tables
Table 3A. N Clock Divider
Input
N1
0 (default)
0
1
1
N0
0 (default)
1
0
1
Divider Value
÷1
÷2
÷4
÷8
Table 3B. nOEA Output Enable
Input
nOEA
0 (default)
1
Output
Q0
Output is enabled
Output is disabled in logic low state
Table 3C. nOEB Output Enable
Input
nOEB
0 (default)
1
Output
Q1, Q2, Q3
Outputs are enabled
Outputs are disabled in logic low state
REVISION 1 12/17/14
3
1.8V LVPECL CLOCK DIVIDER
8P73S674 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Electrical Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs
Input Current, IN, nIN
V
T
Current, I
VT
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Junction Temperature
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
±30mA
±60mA
50mA
100mA
125C
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 1.8V ±0.15V, T
A
= -40°C to +85°C
Symbol
V
CC
I
CC
Parameter
Core Supply Voltage
Power Supply Current
Outputs Unloaded
Test Conditions
Minimum
1.65
Typical
1.8
62
Maximum
1.95
73
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 1.8V ±0.15V, T
A
= -40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
Input Low
Current
N0, N1,
nOEA, nOEB
N0, N1,
nOEA, nOEB
V
CC
= 1.95V, V
IN
= 1.95V
V
CC
= 1.95V, V
IN
= 0V
-10
Test Conditions
Minimum
1.2
-0.3
Typical
Maximum
1.8
0.3
150
Units
V
V
µA
µA
Table 4C. Differential Input DC Characteristics,
V
CC
= 1.8V ±0.15V, T
A
= -40°C to +85°C
Symbol
R
IN
I
IN
Parameter
Differential Input
Resistance
Input Current
IN, nIN
IN, nIN
Test Conditions
Across IN and nIN with VT floated
Minimum
70
Typical
100
Maximum
130
25
Units
mA
1.8V LVPECL CLOCK DIVIDER
4
REVISION 1 12/17/14
8P73S674 DATA SHEET
Table 4D. LVPECL DC Characteristics,
V
CC
= 1.8V ±0.15V, T
A
= -40°C to +85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage
1
Output Low Voltage
1
Peak-to-Peak Output
Voltage Swing
1
0.6
Test Conditions
Minimum
V
CC
– 1.1
Typical
Maximum
V
CC
– 0.75
V
CC
– 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50 to GND.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 1.8V ±0.15V, T
A
= -40°C to +85°C
1
,
2
Symbol
V
PP
V
DIFF_IN
V
CMR
Parameter
Input Voltage Swing
Differential Input
Voltage Swing
Common Mode Input
Voltage
3
IN, nIN
IN, nIN
IN, nIN
N = ÷1
f
OUT
Output Frequency, Q[3:0]
N = ÷2
N = ÷4
N = ÷8
f
IN
tsk(o)
t
PD
tsk(pp)
t
R
/ t
F
tjit(Ø)
tjit(Ø)
odc
Input Frequency, IN, nIN
Output Skew
4, 5
Propagation Delay
Part-to-Part Skew
4, 6
Output
Rise/Fall Time
Phase Jitter Noise Floor, >100kHz
offset
7
Additive Phase Noise, RMS
Output Duty Cycle
10%-90%
20%-80%
any Q, f
OUT
= 1000MHz
122.88 MHz; 1kHz-40MHz
122.88 MHz; 12kHz-20MHz
50% Input Duty Cycle
45
270
150
-153
100
60
50
180
120
55
N = ÷1
N = ÷2, ÷4, ÷8
200
400
40
Test Conditions
Minimum
0.2
0.4
0.9
Typical
Maximum
1
2
V
CC
–V
PP
/2
1000
500
250
125
1000
100
600
900
500
410
220
Units
V
V
V
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
dBc/Hz
fs
fs
%
NOTE 1: Outputs terminated with 50 to GND.
NOTE 2: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 3: Common mode input voltage is defined as the signal crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 6: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the output differential
crosspoints.
NOTE 7: VCMR is set to 1.12V.
REVISION 1 12/17/14
5
1.8V LVPECL CLOCK DIVIDER
51单片机
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