TMP86C407NG
The information contained herein is subject to change without notice. 021023 _ D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the
“Handling
Guide for
Semiconductor Devices,” or
“TOSHIBA
Semiconductor Reliability Handbook” etc. 021023_A
The Toshiba products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B
The products described in this document shall not be used or embedded to any downstream products
of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of TOSHIBA or others. 021023_C
The products described in this document may include products subject to the foreign exchange and
foreign trade laws. 021023_F
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2006 TOSHIBA CORPORATION
All Rights Reserved
Caution in Setting the UART Noise Rejection Time
When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com-
bination "O" is available but please do not select the combination "–".
The transfer clock generated by timer/counter interrupt is calculated by the following equation :
Transfer clock [Hz] = Timer/counter source clock [Hz]
÷
TTREG set value
RXDNC setting
BRG setting
Transfer
clock [Hz]
01
(Reject pulses shorter
than 31/fc[s] as noise)
O
–
O
O
O
10
(Reject pulses shorter
than 63/fc[s] as noise)
O
–
–
O
O
11
(Reject pulses shorter
than 127/fc[s] as
noise)
–
–
–
–
O
00
(No noise rejection)
000
110
(When the transfer clock gen-
erated by timer/counter inter-
rupt is the same as the right
side column)
fc/13
fc/8
fc/16
fc/32
O
O
O
O
O
The setting except the above
2008-08-29
TMP86FM29
Comparison table of TMP86C829B/H29B/M29B/PM29A/PM29B/C929AXB and TMP86FM29
TMP86C829B
TMP86CH29B
TMP86CM29B
ROM
8 K (Mask ROM)
16 K (Mask ROM)
32 K (Mask ROM)
512
1.5 K
1.5 K
42 pin
5 pin
10-bit AD converter
×
8 ch
18-bit timer
×
1 ch
8-bit timer
×
4 ch
8-bit UART / SIO
×
1 ch
32 seg
×
4 com
4 ch
1.8 to 5.5 V at 4.2 MHz
2.7 to 5.5 V at 8 MHz
4.5 to 5.5 V at 16 MHz
−40
to 85℃
−
N/A
1.8 to 5.25 V at 4.2 MHz
2.7 to 5.25 V at 8 MHz
4.5 to 5.25 V at 16 MHz
0 to 60°C
TMP86PM29A
TMP86PM29B
TMP86C929AXB
(Emulation chip)
(Note 3)
−
TMP86FM29F
Difference
32 K (OTP)
32 K (Flash)
RAM
I/O
External
Interrupt
AD Converter
Timer Counter
Serial Interface
LCD
Key-on
Wakeup
Operating
Voltage
in MCU Mode
Operating
Temperature
in MCU Mode
Writing to
Flash Memory
CPU Wait (Note 1)
1.5 K
−
42 pin (MCU part)
2K
42 pin
5 pin
10-bit AD converter
×
8 ch
18-bit timer
×
1 ch
8-bit timer
×
4 ch
8-bit UART / SIO
×
1 ch
32 seg
×
4 com (Note 2)
4 ch
1.8 to 3.6 V at 4.2 MHz (External clock)
1.8 to 3.6 V at 8 MHz (Resonator)
2.7 to 3.6 V at 16 MHz
−40
to 85°C
2.7 to 3.6V at 16 MHz
25°C
±
5°C
Available
Note 1: The CPU wait is a CPU halt function for stabilizing of power supply of Flash memory. The CPU wait
period is as follows. In the CPU wait period except RESET, CPU is halted but peripheral functions
are not halted. Therefore, if the interrupt occurs during the CPU wait period, the interrupt latch is set.
In this case, if the IMF has been set to “1”, the interrupt service routine is executed after CPU wait
period. For details refer to 2.14 “Flash Memory” in TMP86FM29 data sheet.
Thus, even if the same software is executed in 86FM29 and 86C829B/H29B/M29B/PM29A/PM29B
/C929AXB, the operation process is not the same. Therefore, when the final operating confirmation
on target application is executed for software development of Mask ROM Product
(86C829B/H29B/M29B), not the Flash product (86FM29) but the OTP product (86PM29A/PM29B)
should be used.
Condition
After reset release
Changing from STOP mode to NORMAL mode
(at EEPCR<MNPWDW>
=
“1”)
Changing from STOP mode to SLOW mode
(at EEPCR<MNPWDW>
=
“1”)
Changing from IDLE0/1/2 mode to NORMAL mode
(at EEPCR<ATPWDW>
=
“0”)
Changing from SLEEP0/1/2 mode to SLOW mode
(at EEPCR<ATPWDW>
=
“0”)
Wait Time
2 /fc[s]
2 /fc[s]
2 /fs[s]
2 /fc[s]
2 /fs[s]
3
10
3
10
10
Halt/Operate
CPU
Halt
Halt
Halt
Halt
Halt
Peripherals
Halt
Operate
Operate
Operate
Operate
2004-03-01
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