NJG1126HB6
2.1GHz Band LNA GaAs MMIC
GENERAL DESCRIPTION
NJG1126HB6 is a LNA IC designed for 2.1GHz band W-CDMA
cellular phone . This IC has the function which bypasses LNA, and
high gain mode or low gain mode can be chosen.
High IIP3 and a low noise are achieved at the High gain mode.
And low current consumption can be achieved at the low gain mode
because LNA enters the state of the standby.
A small and thin package of USB8 is adopted.
FEATURES
Low voltage operation
Low CTL voltage operation
Low current consumption
High gain
Low noise figure
Pin at 1dB Gain Compression point
High input IP3
Small package
PACKAGE OUTLINE
NJG1126HB6
+2.7V typ.
+1.85V typ.
2.2mA typ.
@V
CTL
=1.85V
1uA typ.
@V
CTL
=0V
16.5dB typ.
@V
CTL
=1.85V, fRF =2140MHz
1.4dB typ.
@V
CTL
=1.85V, fRF =2140MHz
-12.0dBm typ. @V
CTL
=1.85V, fRF =2140MHz
+11.0dBm typ. @V
CTL
=0V, fRF=2140MHz
0dBm typ.
@V
CTL
=1.85V, fRF =2140MHz
+16.0dBm typ. @V
CTL
=0V, fRF=2140MHz
USB8-B6 (Package size: 1.5mmx1.5mmx0.55mm typ.)
PIN CONFIGURATION
(Top View)
GND
RFIN
4
RFOUT
5
3
GND
GND
6
Bias
Circuit
Logic
Circuit
2
Pin Connection
1. V
INV
2. GND
3. RF OUT
4. GND
5. RF IN
6. GND
7. V
CTL
8. GND
VCTL
VINV
7
GND
1
8
1 Pin INDEX
Note: Specifications and description listed in this catalog are subject to change without prior notice.
Ver.2007-02-25
-1-
NJG1126HB6
ABSOLUTE MAXIMUM RATINGS
T
a
=+25°C, Z
s
=Z
l
=50Ω
PARAMETERS
Supply voltage
Inverter supply voltage
Control voltage
Input power
Power dissipation
Operating temperature
Storage temperature
SYMBOL
V
DD
V
INV
V
CTL
Pin
P
D
T
opr
T
stg
V
DD
=2.85V
on PCB board, Tjmax=150°C
CONDITIONS
RATINGS
5.0
5.0
5.0
+15
135
-40~+85
-55~+150
UNITS
V
V
V
dBm
mW
°C
°C
ELECTRICAL CHARACTERISTICS 1 (DC)
(General Conditions: V
DD
=V
INV
=2.85V, T
a
=+25°C, Z
s
=Z
l
=50Ω)
PARAMETERS
Operating voltage
Inverter supply voltage
Control voltage (High)
Control voltage (Low)
Operating current1
(LNA High Gain Mode)
Operating current2
(LNA High Gain Mode)
Inverter current1
(LNA High Gain Mode)
Inverter current2
(LNA High Gain Mode)
Control current
SYMBOL
V
DD
V
INV
V
CTL
(H)
V
CTL
(L)
I
DD
1
I
DD
2
I
INV
1
I
INV
2
I
CTL
RF OFF, V
CTL
=1.85V
RFOFF, V
CTL
=0V
RF OFF, V
CTL
=1.85V
RF OFF, V
CTL
=0V
RF OFF, V
CTL
=1.85V
CONDITIONS
MIN
2.5
2.5
1.5
0
-
-
-
-
-
TYP
2.85
2.85
1.85
0
2.2
1
90
16
5
MAX
3.2
3.2
V
INV
+0.3
UNITS
V
V
V
V
mA
uA
uA
uA
uA
0.3
3.2
5
150
50
20
-2-
NJG1126HB6
ELECTRICAL CHARACTERISTICS 2 (LNA High Gain Mode)
(General Conditions: V
DD
=V
INV
=2.7V, V
CTL
=1.85V, freq=2140MHz, T
a
=+25°C, Z
s
=Z
l
=50Ω)
PARAMETERS
Small signal gain1
Noise figure1
1dB gain compression
output power1
3rd order Input
Intercept Point1
RF IN VSWR1
RF OUT VSWR1
SYMBOL
Gain1
NF1
P
-1dB(IN)
1
IIP3_1
VSWR
I
1
VSWR
o
1
f1=fRF, f2=fRF+100kHz,
Pin=-32dBm
Exclude PCB & connector losses
(IN: 0.09dB)
CONDITIONS
MIN
15.0
-
-15.5
-5.0
-
-
TYP
16.5
1.4
-12.0
0
1.6
1.5
MAX
19.0
1.7
-
-
2.2
2.2
UNITS
dB
dB
dBm
dBm
-
-
ELECTRICAL CHARACTERISTICS 2 (LNA Low Gain Mode)
(General Conditions: V
DD
=V
INV
=2.7V, V
CTL
=0V, freq=2140MHz, T
a
=+25°C, Z
s
=Z
l
=50Ω)
PARAMETERS
Small signal gain2
Noise figure2
1dB gain compression
output power2
3rd order Input
Intercept Point2
RF IN VSWR2
RF OUT VSWR2
SYMBOL
Gain2
NF2
P
-1dB(IN)
2
IIP3_2
VSWR
I
2
VSWR
o
2
F1=fRF, f2=fRF+100kHz,
Pin=-16dBm
Exclude PCB & connector losses
(IN: 0.09dB)
CONDITIONS
MIN
-10.0
-
+4.5
0
-
-
TYP
-7.0
7.0
+11.0
+16.0
1.5
1.5
MAX
-5.5
10.0
-
-
2.0
2.0
UNITS
dB
dB
dBm
dBm
-
-
-3-
NJG1126HB6
TERMINAL INFOMATION
No.
1
2
SYMBOL
VINV
GND
DESCRIPTION
Supply voltage terminal for internal logic circuit (inverter). Please place a bypass
capacitor between this and GND for avoiding RF noise from outside.
Ground terminal.
RF signal comes out from this terminal, and goes through an external matching circuit
connected to this. Inductor L3 as shown in the application circuit is a part of an external
matching circuit, and also provide DC power to LNA. Capacitor C2 as shown in the
application circuit is a bypass capacitor.
Ground terminal.
RF input signal is input to this terminal through an external matching circuit connected to
this terminal. A DC blocking capacitor is not required.
Ground terminal.
Control port. A logic control signal is required to select High or Low gain mode of LNA.
This terminal is set to more than +1.5V of logical high level for High gain mode of LNA,
and set to 0~+0.3V of logical low level for Low gain mode.
Ground terminal.
3
RFOUT
4
5
6
GND
RFIN
GND
7
VCTL
8
GND
CAUTION
1) Ground terminal (No.2, 4, 6, 8) should be connected to the ground plane as close as possible for
excellent RF performance, because distance to GND makes parasitic inductance.
TRUTH TABLE
“H”=V
CTL
(H), “L”=V
CTL
(L)
V
CTL
L
H
Gain Mode
Low
High
LNA
bypass
pass
-4-
NJG1126HB6
ELECTRICAL CHARACTERISTICS (LNA High Gain Mode)
General Conditions: Ta=+25°C, V
DD
=V
INV
=2.7V, V
CTL
=1.85V, Zs=Zl=50Ω
Pout vs. Pin
10
5
0
(f=2140MHz)
20
18
16
Gain, I
DD
vs. Pin
(f=2140MHz)
7
6
5
Gain
Pout (dBm)
Gain (dB)
-5
-10
-15
P-1dB(IN)=-12.0dBm
-20
-25
-40
14
12
10
8
6
-40
P-1dB(IN)=-12.0dBm
I
DD
4
3
2
1
0
-30
-20
-10
0
10
-30
-20
-10
0
10
Pin (dBm)
Pin (dBm)
Pout, IM3 vs. Pin
20
(f1=2140MHz, f2=f1+100kHz)
22
20
OIP3, IIP3 vs. frequency
(f1=2.1~2.2GHz, f2=f1+100kHz, Pin=-32dBm)
12
10
0
Pout
18
Pout, IM3 (dBm)
OIP3 (dBm)
16
14
12
6
4
2
-40
-60
IIP3
IM3
10
IIP3=+0.8dBm
8
6
2.1
0
-2
-4
2.2
-80
-100
-40
-30
-20
-10
0
10
2.12
2.14
2.16
2.18
Pin (dBm)
frequency (GHz)
NF vs. frequency
4
3.5
(f=2~2.3GHz)
20
k factor vs. frequency
(f=50M~20GHz)
(Exclude PCB, Connector Losses)
15
Noise Figure (dB)
3
2
k factor
2.5
10
NF
1.5
1
0.5
0
2
2.05
2.1
2.15
2.2
2.25
2.3
5
0
0
5
10
15
20
frequency (GHz)
frequency (GHz)
-5-
IIP3 (dBm)
-20
OIP3
8
I
DD
(mA)
Pout
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
