SA58635
2
×
25 mW class-G stereo headphone driver with I
2
C-bus
volume control
Rev. 01 — 26 March 2010
Product data sheet
1. General description
The SA58635 is a stereo, class-G headphone driver with I
2
C-bus volume control. The
I
2
C-bus control allows maximum flexibility with digital volume control, independent
channel enable and mute control.
The output of the SA58635 is referenced around true ground zero. It is designed to
operate at the low supply current of 1.5 mA making it battery friendly. A unique power
management technique provides class-G power efficiency by using a buck converter to
step down the battery supply from a typical lithium ion battery (4.8 V to 2.3 V). Efficiency is
further increased by allowing the output amplifier/driver to operate at multiple voltage rails
based on the output/input swing.
The SA58635 delivers 2
×
25 mW minimum into 16
Ω
and 32
Ω
loads. The SA58635
provides thermal shutdown and self limiting current protection.
The SA58635 is a high fidelity HP driver amplifier with a S/N of 100 dB minimum. An
excellent PSRR of more than 100 dB, differential input circuit topology allows for
maximum noise immunity in the noisy mobile phone environment.
The SA58635 is available in a 16-bump WLCSP (Wafer Level Chip-Size Package) making
it ideal choice for cellular handsets and portable media players.
2. Features
Power supply range: 2.3 V to 5.5 V
High efficiency employing class-G dynamic power management
2
×
25 mW into 16
Ω
or 32
Ω
at THD+N = 1 %
Very low THD+N at 0.02 % at V
O
of 0.7V
o(RMS)
and R
L
of 47
Ω
Integrated charge pump to eliminate DC blocking capacitors, reduce cost and PCB
space while improving low frequency audio fidelity
Excellent PSRR: > 100 dB
S/N performance of 100 dB minimum
Low supply current: 1.5 mA typical
Low shutdown current: 5
μA
maximum
I
2
C-bus interface for
−59
dB to
±4
dB volume control, independent channel enable,
mute and software shutdown
Self limiting current with thermal protection and ground loop noise suppression
Pop-and-click suppression
Available in 1.7 mm
×
1.7 mm 16-bump WLCSP
NXP Semiconductors
SA58635
2
×
25 mW class-G stereo headphone driver
3. Applications
Wireless and cellular handsets
Portable media players
Portable DVD player
Notebook PC
High fidelity applications
4. Ordering information
Table 1.
Ordering information
Package
Name
SA58635UK
WLCSP16
Description
wafer level chip-size package; 16 balls; 1.7
×
1.7
×
0.56 mm
Version
SA58635UK
Type number
5. Block diagram
SW
AVDD
HPVDD
THERMAL/SHORT-CIRCUIT
PROTECTION
BUCK
CONVERTER
SA58635
INLP
OUTL
INLN
CLASS-G CONTROL
SGND
INRP
OUTR
INRN
HPVSS
CHARGE
PUMP
CPN
CPP
VOLUME
CONTROL
AGND
I
2
C-BUS
INTERFACE
002aad931
SCL
SDA
Fig 1.
Block diagram of SA58635
SA58635_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 26 March 2010
2 of 30
NXP Semiconductors
SA58635
2
×
25 mW class-G stereo headphone driver
6. Pinning information
6.1 Pinning
SA58635UK
1
2
3
4
ball A1
index area
A
B
1
C
A
B
D
C
D
002aaf273
2
AVDD
CPP
HPVSS
SCL
3
OUTL
HPVDD
SGND
OUTR
4
INLN
INLP
INRP
INRN
002aad933
SW
AGND
CPN
SDA
Transparent top view
Transparent top view
Fig 2.
Pin configuration for WLCSP16
Fig 3.
Ball mapping for WLCSP16
6.2 Pin description
Table 2.
Symbol
SW
AVDD
OUTL
INLN
AGND
CPP
HPVDD
INLP
CPN
HPVSS
SGND
INRP
SDA
SCL
OUTR
INRN
Pin description
Pin
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
Description
buck converter switching mode
analog supply; same as battery
headphone left channel output
left channel negative differential input
analog supply ground
charge pump positive capacitor
buck converter output voltage
left channel positive differential input
charge pump negative capacitor
charge pump negative output voltage
ground sense; connect to headphone jack ground
right channel positive differential input
I
2
C-bus serial data
I
2
C-bus serial clock
headphone right channel output
right channel negative differential input
SA58635_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 26 March 2010
3 of 30
NXP Semiconductors
SA58635
2
×
25 mW class-G stereo headphone driver
7. Functional description
Refer to
Figure 1 “Block diagram of SA58635”.
7.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing.
The SA58635 responds to two slave addresses: 1100 000xb for standard accesses and
the General Call writes (0000 0000b) for software reset. The last bit of the address byte
defines the operation to be performed. When set to logic 1 a read is selected, while a
logic 0 selects a write operation.
When a reset of the I
2
C-bus needs to be performed by the master, the master will write to
the General Call address followed by a write of the reset command (0000 0110b). When a
General Call reset command is sent by the master, the SA58635 will respond with an
acknowledge and execute a reset to the digital logic. This will return the register set and
the volume controls to the Power-On Reset (POR) values.
7.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the SA58635, which will be stored in the Control register.
The lowest 3 bits are used as a pointer to determine which register will be accessed
(D[2:0]). The remaining bits are not used and are ignored.
7.3 Register definitions
Table 3.
Register
number
(hex)
00
01
02
03
04
05
06
07
Register summary
Name
Type
Function
-
MODE1
VOLCTL
HIZ
ID
-
TEST1
-
-
read/write
read/write
read/write
read only
-
read/write
read/write
Reserved; this address is empty and will be NACKed.
Contains the left and right channel amplifier enable bits,
thermal status and the software shutdown bit.
Volume setting and mute left and right bits.
High-impedance controls for left and right channel.
Vendor Identification and chip version number.
Reserved; this address is empty and will be NACKed.
This register is for manufacturing test.
Reserved; this register is empty and will be NACKed.
SA58635_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 26 March 2010
4 of 30
NXP Semiconductors
SA58635
2
×
25 mW class-G stereo headphone driver
7.3.1 MODE1 register, MODE1
Table 4.
MODE1 - Mode register 1 (address 01h) bit description
Legend: * default value.
Bit
7
Symbol
HP_EN_L
Access
R/W
Value
0*
1
6
HP_EN_R
R/W
0*
1
5
4
3
2
1
0
-
-
-
-
THERMAL
SWS
read only
read only
read only
read only
read only
R/W
0*
0*
0*
0*
0*
1
0*
1
Description
Left channel inactive. A zero will turn off the left
channel.
Left channel active.
Right channel inactive. A zero will turn off the right
channel.
Right channel active.
Reserved; always reads back as a 0.
Reserved; always reads back as a 0.
Reserved; always reads back as a 0.
Reserved; always reads back as a 0.
Device is operating normally.
Device is in thermal shutdown.
Device is enabled.
Software shutdown; charge pump is disabled.
7.3.2 Volume control register, VOLCTL
Table 5.
VOLCTL - Volume control register (address 02h) bit description
Legend: * default value.
Bit
7
6
Symbol
MUTEL
MUTER
Access
R/W
R/W
Value
0
1*
0
1*
5 to 1
0
VOL[4:0]
-
R/W
read only
0*
0*
Description
A zero indicates that the left channel is not muted.
Left channel is muted.
A zero indicates that the right channel is not
muted.
Right channel is muted.
These bits indicate the volume on the outputs per
the gain table shown in
Table 9.
This bit is reserved and will always return a zero.
7.3.3 High-impedance register, HIZ
Table 6.
HIZ - High-impedance register (address 03h) bit description
Legend: * default value.
Bit
7 to 2
1
0
Symbol
-
HIZL
HIZR
Access
read only
R/W
R/W
Value
0*
0*
1
0*
1
Description
Unused; always returns 0.
Device outputs are not in high-impedance.
Device outputs are in high-impedance.
Device outputs are not in high-impedance.
Device outputs are in high-impedance.
SA58635_1
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 01 — 26 March 2010
5 of 30
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