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74LVXC4245TTR

产品描述Bus Transceivers Octal Bus Tansceiver
产品类别逻辑    逻辑   
文件大小183KB,共14页
制造商ST(意法半导体)
官网地址http://www.st.com/
标准
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74LVXC4245TTR概述

Bus Transceivers Octal Bus Tansceiver

74LVXC4245TTR规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称ST(意法半导体)
零件包装代码TSSOP
包装说明TSSOP, TSSOP24,.25
针数24
Reach Compliance Codecompliant

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74LVXC4245
OCTAL DUAL SUPPLY BUS TRANSCEIVER
s
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 6.5ns (MAX.) at
V
CCA
= 5.0V, V
CCB
= 5.0V
LOW POWER DISSIPATION:
I
CCA
= I
CCB
= 5µA(MAX.) at T
A
=25°C
LOW NOISE: V
OLP
=0.3V (TYP.) at
V
CCA
=5.0V V
CCB
=3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CCA
(OPR) = 4.5V to 5.5V (1.2V Data Retention)
V
CCB
(OPR) = 2.7V to 5.5V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES C4245
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74LVXC4245 is a dual supply 8 bit
configurable low voltage CMOS OCTAL BUS
TRANSCEIVER fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. Designed for use as an interface
between a 5V bus and a 3.3V to 5V bus in a mixed
5V/3.3V supply systems, it achieves high speed
operation while maintaining the CMOS low power
dissipation.
Figure 1: Pin Connection And IEC Logic Symbols
O
et
l
so
b
ro
P
e
uc
d
s)
t(
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G can be used to
disable the device so that the buses are effectively
isolated.
The A-port interfaces with the 5V bus, the B-port
with the 3.3V to 5V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
O
-
so
b
te
le
ro
P
uc
d
s)
t(
T&R
74LVXC4245MTR
74LVXC4245TTR
August 2004
Rev. 4
1/14

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